ARM and Cadence Design Systems, Inc. today announced the tape-out of the first 14-nanometer test chip implementation of the energy-efficient ARM Cortex-A7 processor.

Designed with a complete Cadence RTL-to-signoff flow, the chip is the first to target Samsung's 14-nanometer FinFET process, accelerating the continuing move to high-density, high-performance and ultra-low power SoCs for future smartphones, tablets and all other advanced mobile devices.

In addition to the ARM Cortex-A7 processor, the test chip includes ARM Artisan standard-cell libraries, next-generation memories, and general purpose IOs. The test chip was designed using a complete Cadence RTL-to-signoff flow including Encounter RTL Compiler, Encounter Test, Encounter Digital Implementation System, Cadence QRC Extraction, Encounter Timing System and Encounter Power System. This achievement is part of a systematic program to enable ARM technology-based SoCs on FinFET technology.

"This is an important milestone in our efforts to enable our silicon partners for continued low-power leadership in future generations of innovative, energy-efficient mobile products," said Dr. Dipesh Patel, vice president and general manager, Physical IP Division at ARM. "Taping out ARMs most energy-efficient applications processor on Samsungs advanced low-power manufacturing process was achieved through the combination of leading-edge technology and R&D excellence, as well as a deep and early collaboration with Samsung and Cadence."

"End consumers are driving the need for better, faster, more connected devices," said Dr. Kyu-Myung Choi, senior vice president of System LSI infrastructure design center, Device Solutions, Samsung Electronics. "Our collaboration with ARM and Cadence allows us to innovate quickly as Samsung develops this new process technology for mobile multimedia applications."

Samsung also worked with Synopsys for the successful tapeout of the first test chip on Samsung's 14LPE process.

"FinFET transistors can deliver lower power consumption and higher device performance, but they also bring tough challenges," said Dr. Kyu-Myung Choi , vice president of System LSI infrastructure design center, Device Solutions, Samsung Electronics. "We chose Synopsys as our FinFET collaboration partner to solve these challenges, because of our successful history together at 20 nanometer and other nodes. We continue to pool our expertise to deliver innovative FinFET solutions."

Synopsys worked with Samsung to develop a test chip that validates Samsung's advanced 14-nm FinFET process as well as Synopsys' DesignWare Embedded Memories using Synopsys' Self-Test and Repair (STAR) Memory System solution. The test chip will enable the correlation of the simulation models to the FinFET process and contains test structures, standard cells, a PLL and embedded SRAMs. The memory instances include high-density SRAMs designed to operate at very low voltages and high-speed SRAMs to validate the process performance.