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Thursday, June 13, 2013
Toshiba Develops First Multi-level-cell Structure MROM cell, 'BiCS' 3D NAND Flash Memory


Toshiba has developed the first MROM cell to offer improved cell current characteristics without any increase in cell size. This advance was achieved by adopting a multi-level-cell structure, which also secures high speed operation.

Seperately, the Japanese company has recently talked about the "BiCS (bit cost scalable)" next-generation NAND flash memory, which stacks memory cells in multiple layers in three-dimensional directions.

MROM's main role is to store the boot loader or firmware. The density of MROM implemented is SoC for such digital applications as smartphones and tablet PCs is increasing year by year, and in order to improve access time it is necessary to halve the MROM cell area with every generation.

In a typical MROM bit cell, a single-level cell, variations in fabrication are increasing as SoC process technology advances, with the narrowing of the channel area of the cell transistors. The result is a slower access time for the 40nm generation than for the previous process generation. Improving access time requires a larger transistor, as a bigger cell area secures a wider channel area.

Toshiba has developed a multi-bit cell that uses twice the area of a standard single level cell, successfully expanding channel width in the cell transistor by three times. This also triples the current characteristic of the cell without any change in the memory capacity per area. It reduces the influence of the variation in fabrication by 42%.

Toshiba has developed of MROM cell with the 40nm process generation and aims to ship SoC for digital applications that implement the cell in 2014.

Details will be presented on June 14 at the 2013 Symposia on VLSI Technology and Circuits, held in Kyoto, Japan, June 11-14, 2013.

BiCS NAND

Toshiba had proposed Bit Cost Scalable (BiCS) technology in 2007 as a three-dimensional memory for the future ultra high density storage devices, which extremely reduce the bit costs by vertically stacking memory arrays with punch and plug process.

At the same event, the company announced that it has applied the BiCS tecchnology to just NAND flash, which is BiCS Flash memory, and established the mass production technology.

One of the features of the BiCS is that multiple layers of memory cells can be formed at one time with multilayer formation and etching technologies.

Akihiro Nitayama from Toshiba Semiconductor & Storage Products Company, said Toshiba made improvements to the original structure to overcome disadvantages such as low operation speed and data retention properties. The company has improved memory cell properties by employing a structure called "P-BiCS." It solved the problem of the cell current degradation caused by an increase in the number of memory cell layers by improving the channel mobility of polysilicon TFT. And it enhanced data retention prope

Nitayama also compared the BiCS with other 3D NAND flash memories being developed by other companies and said that the BiCS is the most promising technology for Tbit-class storage devices in terms of the number of manufacturing processes, memory cell area, disturbance resistance, etc.

Toshiba is expected to start to ship samples of the BiCS within 2013.

3D ReRAMs (resistive random-access memories) and PRAMs (phase-change random access memories) using process technologies similar to the BiCS technology have been recently introduced.


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