TSMC has extended its collaboration with Mentor Graphics on the Xpedition Enterprise platform in conjunction with the Calibre platform for the design and verification of TSMC's InFO (Integrated Fan-Out) packaging technology for multi-chip and chip-DRAM integration applications.
Mentor developed new Xpedition functionality specifically to support InFO and enable the IC package designer to complete design tasks to TSMC specification.
"TSMC's InFO packaging supports diverse industry needs," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "An InFO solution based upon package tools such as the Xpedition Enterprise and sign-off Calibre platforms from Mentor Graphics helps our customers meet their time-to-market goals."
The Mentor Graphics Xpedition Enterprise platform is a used design flow for PCB, IC package, and multi-board system-level design, from architecture authoring through implementation to manufacturing execution. The integration of the Xpedition Enterprise platform for design with the HyperLynx tool suite and Calibre platform for analysis and verification provides advantages to designers implementing InFO designs:
- Xpedition generates InFO layouts meeting TSMC design rule requirements;
- Streamlined in-design InFO-specific manufacturing verification using HyperLynx DRC expedites time to closure, reducing DRC iterations during the design stage;
- Calibre DRC, LVS, and 3DSTACK solutions provide sign-off-level die and InFO package DRC and layout vs. schematic (LVS) inter-die connectivity verification to ensure TSMC-required accuracy and a DRC-clean GDS to improve first-time success rates;
- Direct highlighting and cross-probing of Calibre tools into packaging design cockpit results reduces time to foundry-ready signoff;
- Integration to thermal analysis and thermally-aware post-layout simulation flows provides early identification of potential heat issues;
- System-level signal path tracing, extraction, simulation, and netlist export ensures complete InFO package signal integrity.