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Wednesday, February 28, 2018
Imec and Cadence Tape Out First 3nm Chip


Imec and Cadence Design Systems are working toward a 3-nm tapeout of a 64-bit processor, aims to produce a working chip later this year using a combination of extreme ultraviolet (EUV) and immersion lithography.

The tapeout project, geared toward advancing 3nm chip design, was completed using extreme ultraviolet (EUV) and 193 immersion (193i) lithography-oriented design rules and the Cadence Innovus Implementation System and Genus Synthesis Solution.

Imec utilized a common industry 64-bit CPU for the test chip with a custom 3nm standard cell library and a TRIM metal flow, where the routing pitch was reduced to 21nm.

Together, Cadence and imec have enabled the 3nm implementation flow to be fully validated in preparation for next-generation design innovation.

The Cadence Innovus Implementation System is a massively parallel physical implementation system that enables engineers to deliver high-quality designs with optimal power, performance and area (PPA) targets. The Cadence Genus Synthesis Solution is a next-generation, high-capacity RTL synthesis and physical synthesis engine that addresses the latest FinFET process node requirements, improving RTL designer productivity.

For the project, EUV and 193i lithography rules were tested to provide the required resolution, while providing PPA comparison under two different patterning assumptions.

"As process dimensions reduce to the 3nm node, interconnect variation becomes much more significant," said An Steegen, executive vice president for semiconductor technology and systems at imec. "Our work on the test chip has enabled interconnect variation to be measured and improved and the 3nm manufacturing process to be validated. Also, the Cadence digital solutions offered everything needed for this 3nm implementation. Due to Cadence's well-integrated flow, the solutions were easy to use, which helped our engineering team stay productive when developing the 3nm rule set."

Imec is starting work on the masks and lithography, initially aiming to use double-patterning EUV and self-aligned quadruple patterning (SAQP) immersion processes. Over time, Imec plans to further optimize the process to use a single pass in the EUV scanner, which will offer a reduction of wafer cost over the full immersion approach. However, this approach has more implementation challenges. As pitch-only scaling becomes a burden in technology node transition, imec's solutions have been complemented by co-optimizing the technology and the design libraries resulting in significantly lower area while lessening the burden in pitch-only scaling. This allows a full node definition with fixed wafer cost increase with more area reduction.

Ultimately, fabs may migrate to upcoming EUV systems with high NA to make 3-nm chips.

TSMC announced in October plans for a 3-nm fab in Taiwan, which is expected to build by 2022.

Besides the finer features, the first two layers of 3-nm chips may use different metalization techniques and metals such as cobalt, said Ryoung-han Kim, an R&D group manager at Imec. The node is also expected to use new transistor designs such as nanowires or nanosheets rather than the FinFETs used in today's 16-nm and finer processes.



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