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Tuesday, November 20, 2012
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Notable Papers at ISSCC 2013
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Samsung, Intel And Nvidia will be among the companies who will present papers at the 2013 IEEE International Solid-State Circuits Conference (ISSCC).
Starting with Samsung, the S. Korean company will present a paper entitled "28nm High-κ Metal-Gate Heterogeneous Quad-Core CPUs for High-Performance and Energy-Efficient Mobile Application Processor."
Samsung's paper described a SoC with two quad-core clusters - an 1.8 GHz cluster geared for high performance apps and a second one running at 1.2 GHz and is tuned for energy efficiency. The new SOC is probably Samsung's implementation of ARM's big.little architecture.
Intel will not describe its upcoming 22-nm Haswell processor or any other processors at ISSCC. The company will present a scalable 64-lane chip-to-chip interconnect with 1 Tbit/s aggregate bandwidth. The link uses multiple 2-16 Gbit/s channels running at power efficiencies of 0.8 to 2.6 pJ/bit in 32nm CMOS with a total bus-level power consumption of 2.6 W.
(Paper: Scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-Lane Parallel I/O in 32nm CMOS.)
Nvidia will not talk directly about the Project Denver SoC. However, the company will describe a 20 Gbit/s serial die-to-die link made in 28-nm CMOS. The link runs on a 0.9 V supply and has power efficiency of 0.54pJ/b. This one could be part of
Project Denver SoC, which will include both ARM and graphics cores and will power a wide range of products.
(Paper: A 0.54pJ/b 20Gb/s Ground-Referenced Single-Ended
Short-Haul Serial Link in 28nm CMOS for Advanced
Packaging Applications)
Another interesting paper will be presented by
China's Institute of Computing Technology, describing a new version of the China-made Godson 3B processor. The 8-core processor is a 32-nm high-K, metal gate part delivering 172.8 Gflops when running at 1.35 GHz at 40W. (Paper: Godson-3B1500: A 32nm 1.35GHz 40W 172.8GFLOPS
8-Core Processor)
Renesas will describe a 28nm High- Metal-Gate communications SoC with an 1.5GHz dual-core application processor and an LTE/HSPA+-capable baseband processor
Texas Instruments and MIT will describe a 200-MHz video decoder implementing the High-Efficiency Video Coding (HEVC) draft standard to deliver 249 Mpixels/s.
AMD, IBM and Oracle will present papers on their Jaguar (Paper: Jaguar: A Next-Generation Low-Power x86-64 Core,) zSeries (Paper: 5.5GHz System z Microprocessor and Multichip Module) and Sparc T5 processors (Paper: A 3.6GHz 16-Core SPARC SoC Processor in 28nm.)
For more information, read the ISSCC 2013 advance program |
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