Friday, March 29, 2024
Search
  
Tuesday, February 7, 2017
 Sony Develops the First 3-Layer Stacked CMOS Image Sensor with DRAM for Smartphones
You are sending an email that contains the article
and a private message for your recipient(s).
Your Name:
Your e-mail: * Required!
Recipient (e-mail): *
Subject: *
Introductory Message:
HTML/Text
(Photo: Yes/No)
(At the moment, only Text is allowed...)
 
Message Text:

Sony has developed the industry's first 3-layer stacked CMOS image sensor with DRAM for smartphones, a device that offers high-speed data readout with minimum distortion in still images, and also enables super slow motion movie shooting.



The new image sensor consists of a DRAM layer added to the conventional 2-layer stacked CMOS image sensor with a layer of back-illuminated structure pixels and a chip affixed with mounted circuits for signal processing.

This nsensor with DRAM delivers fast data readout speeds, making it possible to capture still images of fast-moving subjects with minimal focal plane distortion as well as super slow motion movies at up to 1,000 frames per second (approximately 8x faster than conventional products) in full HD (1920x1080 pixels).

In order to realize the high-speed readout, the circuit used to convert the analog video signal from pixels to a digital signal has been doubled from a 2-tier construction to a 4-tier construction in order to improve processing ability. Although there are speed limitations in the interface specifications for outputting signals from image sensors to other LSIs, this sensor uses DRAM to store signals read at high speed temporarily, enabling data to be output at an optimal speed for the standard specifications. As a result, the product is capable of reading one still image of 19.3 million pixels in only 1/120 of a second (approximately 4x faster than conventional products), thereby supporting high-speed image capture.

The sensor also includes solutions for the various technical problems inherent in the design, for instance, reducing the noise generated between the circuits on each of the three layers.

These development results were announced at the International Solid-State Circuits Conference (ISSCC) which started on Sunday, February 5, 2017 in San Francisco.

Specifications

  • Effective pixel count: 5520 (H) x 3840 (V) 21.2 megapixels
  • Image size: Diagonal 7.73mm (Type 1/2.3)
  • Unit cell size: 1.22µm (H) x 1.22µm (V)
  • Frame rate:
    • Still images: 30fps 4:3 19.3 megapixels / 16:9 17.1 megapixels
    • Movies:
      • 60fps: 4K (3840 x 2160)
      • 240fps: Full HD / 720p
  • Reading speed: 8.478 ms (4:3 19.3 megapixels) / 6.962 ms (16:9 17.1 megapixels)
  • Power supply: 2.5V / 1.8V / 1.1V
  • Image format: Bayer RAW
  • Output: MIPI (CSI2) D-PHY 2.2Gbps/lane / C-PHY 2.0Gsps/lane
  • DRAM capacity: 1G bit
 
Home | News | All News | Reviews | Articles | Guides | Download | Expert Area | Forum | Site Info
Site best viewed at 1024x768+ - CDRINFO.COM 1998-2024 - All rights reserved -
Privacy policy - Contact Us .