The PCI Express 5.0, Version 0.7 is available for PCI-SIG members to review in the member workspace. The new specification will deliver high-performance 32GT/s data rates and flexible lane configurations-all while prioritizing low power. Additional features include:

• Delivers higher signaling rates that enable narrower links to be used, supporting multiple applications in a variety of form factors
• Support for high-end networking solutions (i.e. 400Gb Ethernet and dual 200Gb/s InfiniBand solutions)
• Accelerator and GPU attachments for high-bandwidth solutions
• Continued use of L1 Sub-states to constrain power consumption during transmission idle periods

With 64GB/s of unidirectional transfer bandwidth, PCIe 5.0 would deliver more bandwidth than dual-channel DDR3 interfaces. Heck, it would deliver more bandwidth than DDR4-3200, though at higher latencies. Currently, GPUs are primarily the only devices that use x16 slots, but quadruple the bandwidth per lane means that x1 and x4 products would still benefit from these gains. High-performance network and SSD solutions could both use the bandwidth, and PCIe 5.0 would put the industry ahead of even Nvidia's high-speed NVLink technology.

With PCIe 4.0 just being finished, motherboard manufacturers could integrate it later this year. If PCI-SIG hits its target goal of a 2019 standard finalization date, PCIe 5.0 could be in-market by 2020 or 2021.

However, the new speeds PCI Express 4.0 and 5.0 are not cheap. And the big trade-off of the higher speeds remains, as signals won't travel as far on existing designs. So, system makers are considering the costs of upgrading boards and connectors, adding chips to amplify signals or redesigning their products to be more compact.

The 700+ member PCI Special Interest Group (SIG) that sets the PCIe standards expects to have some ideas for dealing with the reach issues. It's the main issue the group is grappling with as it prepares a 0.9 version of the 5.0 standard expected by October.