PCIe Base 3.0 Specification Finalized
The PCI-SIG, the industry organization chartered to develop and manage the PCI standard, today announced that the release of the PCI Express Base 3.0 specification.
This specification describes the PCI Express architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.
The goal is to enable such devices from different vendors to inter-operate in an open architecture. The specification is intended as an enhancement to the PCI architecture spanning multiple market segments; Clients (Desktops and Mobile), Servers (Standard and Enterprise), and Embedded and Communication devices. The specification allows system OEMs and peripheral developers adequate room for product versatility and market differentiation without the burden of carrying obsolete interfaces or losing compatibility.
PCIe 3.0 offers a bit rate of 8GT/s - doubled over PCIe 2.0 - as well as optimizations for enhanced signaling and data integrity, including transmitter and receiver equalization, PLL improvements, clock data recovery, and channel enhancements for currently supported topologies.
The PCIe 3.0 specification extends the data rate to 8 GT/s in a manner compatible with the existing PCIe 1.x and 2.x specifications and products that support 2.5 and 5 GT/s signaling. PCI-SIG claims that this bit rate represents the most optimum tradeoff between manufacturability, cost, power, complexity and compatibility. Based on this data rate expansion, it is possible for products designed to the PCIe 3.0 architecture to achieve bandwidth near 1 gigabyte per second (GB/s) in one direction on a single-lane (x1) configuration and scale to an aggregate approaching 32 GB/s on a sixteen-lane (x16) configuration. The new 128b/130b encoding scheme also allows near 100% efficiency, offering a 25% efficiency increase for 8 GT/s as compared to the 8b/10b efficiency of previous versions, which enables the doubled bandwidth.
The goal is to enable such devices from different vendors to inter-operate in an open architecture. The specification is intended as an enhancement to the PCI architecture spanning multiple market segments; Clients (Desktops and Mobile), Servers (Standard and Enterprise), and Embedded and Communication devices. The specification allows system OEMs and peripheral developers adequate room for product versatility and market differentiation without the burden of carrying obsolete interfaces or losing compatibility.
PCIe 3.0 offers a bit rate of 8GT/s - doubled over PCIe 2.0 - as well as optimizations for enhanced signaling and data integrity, including transmitter and receiver equalization, PLL improvements, clock data recovery, and channel enhancements for currently supported topologies.
The PCIe 3.0 specification extends the data rate to 8 GT/s in a manner compatible with the existing PCIe 1.x and 2.x specifications and products that support 2.5 and 5 GT/s signaling. PCI-SIG claims that this bit rate represents the most optimum tradeoff between manufacturability, cost, power, complexity and compatibility. Based on this data rate expansion, it is possible for products designed to the PCIe 3.0 architecture to achieve bandwidth near 1 gigabyte per second (GB/s) in one direction on a single-lane (x1) configuration and scale to an aggregate approaching 32 GB/s on a sixteen-lane (x16) configuration. The new 128b/130b encoding scheme also allows near 100% efficiency, offering a 25% efficiency increase for 8 GT/s as compared to the 8b/10b efficiency of previous versions, which enables the doubled bandwidth.
