Intel Introduces Xeon Phi Brand for Products Based on Many Integrated Core Architecture
At the International Supercomputing Conference, Intel today announced that Intel Xeon Phi is the new brand name for all future Intel Many Integrated Core Architecture (Intel MIC architecture) based products.
Available by the end of 2012, the first generation of Intel Xeon Phi product family (coprocessors codenamed "Knights Corner") will complement the existing Intel Xeon processor E5-2600/4600 product families and promise to deliver new levels of performance for parallel workloads. While the first generation primarily targets high performance computing (HPC), future generations of Intel Xeon Phi products will also address enterprise datacenters and workstations.
"As we add Intel Xeon Phi products to our portfolio, scientists, engineers and IT professionals will experience breakthrough levels of performance to effectively address challenges ranging from climate change to risk management. This is the next step of Intel's commitment to achieve exascale-level computation by 2018, and create a unique technology category that delivers unprecedented performance for today's highly parallel applications," said Raj Hazra, Intel Corporation VP and general manager of the Technical Computing at Data Center and Connected Systems Group.
Intel claims that the new Intel Xeon Phi coprocessor's will be easy to use since they will take advantage of familiar programming models, techniques and developer tools available with Intel architecture. Beyond its compatibility with x86 programming models, the Intel Xeon Phi coprocessor will be visible to applications as an HPC-optimized, highly-parallel, separate compute node that runs its own Linux-based operating system independent of the host OS. This feature allows more flexibility when implementing cluster solutions that are not available with alternative graphics accelerator-based technologies.
Made with Intel's 22nm, 3-D tri-gate transistors, the Intel Xeon Phi coprocessor, available in a PCIe form factor, contains more than 50 cores and a minimum of 8GB of GDDR5 memory. It also features 512b wide SIMD support that improves performance by enabling multiple data elements to be processed with a single instruction.
Last year Intel showed a live demonstration of the single Knights Corner coprocessor delivering over 1 TeraFLOPs (1 trillion floating point operations per second) of double precision real life performance, as measured by DGEMM. At ISC'12 Intel demonstrated the same performance of more than 1 TeraFLOPs per node but measured by the Linpack (Rmax) benchmark. By comparison, in 1997, it took more than 9000 Intel Pentium processors inside the ASCII RED supercomputer to break the 1 TeraFLOPs barrier.
While initial production product shipments are planned for the second half of 2012, Intel has announced that the first Intel Xeon Phi coprocessor-based development cluster is up and running and ranked 150th on the Top500 list, delivering 118 TFLOPs of performance.
Intel says htat 44 manufacturers including Bull, Cray, Dell, HP, IBM, Inspur, SGI and NEC will support the new processors.
Due to power-on in early 2013, the first Petascale class supercomputer powered by a combination of the Intel Xeon processor E5 family and Intel Xeon Phi coprocessors will be "Stampede."
"As we add Intel Xeon Phi products to our portfolio, scientists, engineers and IT professionals will experience breakthrough levels of performance to effectively address challenges ranging from climate change to risk management. This is the next step of Intel's commitment to achieve exascale-level computation by 2018, and create a unique technology category that delivers unprecedented performance for today's highly parallel applications," said Raj Hazra, Intel Corporation VP and general manager of the Technical Computing at Data Center and Connected Systems Group.
Intel claims that the new Intel Xeon Phi coprocessor's will be easy to use since they will take advantage of familiar programming models, techniques and developer tools available with Intel architecture. Beyond its compatibility with x86 programming models, the Intel Xeon Phi coprocessor will be visible to applications as an HPC-optimized, highly-parallel, separate compute node that runs its own Linux-based operating system independent of the host OS. This feature allows more flexibility when implementing cluster solutions that are not available with alternative graphics accelerator-based technologies.
Made with Intel's 22nm, 3-D tri-gate transistors, the Intel Xeon Phi coprocessor, available in a PCIe form factor, contains more than 50 cores and a minimum of 8GB of GDDR5 memory. It also features 512b wide SIMD support that improves performance by enabling multiple data elements to be processed with a single instruction.
Last year Intel showed a live demonstration of the single Knights Corner coprocessor delivering over 1 TeraFLOPs (1 trillion floating point operations per second) of double precision real life performance, as measured by DGEMM. At ISC'12 Intel demonstrated the same performance of more than 1 TeraFLOPs per node but measured by the Linpack (Rmax) benchmark. By comparison, in 1997, it took more than 9000 Intel Pentium processors inside the ASCII RED supercomputer to break the 1 TeraFLOPs barrier.
While initial production product shipments are planned for the second half of 2012, Intel has announced that the first Intel Xeon Phi coprocessor-based development cluster is up and running and ranked 150th on the Top500 list, delivering 118 TFLOPs of performance.
Intel says htat 44 manufacturers including Bull, Cray, Dell, HP, IBM, Inspur, SGI and NEC will support the new processors.
Due to power-on in early 2013, the first Petascale class supercomputer powered by a combination of the Intel Xeon processor E5 family and Intel Xeon Phi coprocessors will be "Stampede."
