TSMC has delivered the complete version of its 5 nanometer (nm) design infrastructure within the Open Innovation Platform (OIP).

This full release can be used for the development of 5nm systems-on-chip (SoC) designs in future mobile and high-performance computing (HPC) applications, targeting 5G and artificial intelligence markets.

Electronic Design Automation (EDA) and IP vendors collaborated with TSMC to develop and validate the design infrastructure, including technology files, process design kits (PDKs), tools, flows and IP, through multiple silicon test vehicles.

TSMC’s 5nm process is already in risk production. Compared with the company's 7nm process, the new scaling features deliver 1.8X logic density and 15% speed gain on an ARM Cortex-A72 core, along with superior SRAM and analog area reduction enabled by the process architecture. TSMC is using the EUV lithography for the new 5nm designs, and says that it is making "excellent progress in yield learning, achieving the best technology maturity at the same corresponding stage as compared to TSMC's previous nodes."

TSMC’s 5nm design infrastructure includes the full versions of the 5nm Design Rule Manual (DRM), SPICE model, process design kits (PDKs) and silicon-validated foundation and interface IP, and also supports a full range of certified EDA tools and design flows.

The latest 5nm PDKs are now available for production design, and include device symbols, Pcells, netlisting and techfiles to enable full design flow from custom design, simulation, implementation, dummy fill, and extraction, to physical verification and signoff.

TSMC collaborated with Cadence, Synopsys, Mentor Graphics, and ANSYS to certify full-line EDA tools through the TSMC OIP EDA Tool Certification Program. The core of the certification program covered silicon-centric EDA tool categories including simulation, physical implementation (Custom Design, APR), timing signoff (STA, Transistor-level STA), Electromigration and IR drop (Gate-level and Transistor-level), physical verifications (DRC, LVS), to RC extractions (RCX).

On top of tool certification, TSMC also added another layer of design flow certification with EDA partners using real designs to validate integrated tool flow for both custom and digital designs. The flow certification focused on critical design implementation requirements using certified tools from TSMC's EDA partners. Certification criteria cover tools’ feature readiness, performance, correlation between implementation and sign-off tools, and design constraints compliance with real designs. In addition, TSMC provided reference flows for both mobile and high-performance computing (HPC) applications which address new design methodologies to improve design quality and efficiency.

TSMC’s 5nm design infrastructure provides an IP Portfolio ready to support the needs of both the advanced mobile segment and HPC applications targeting 5nm process. The Foundation IP includes high-density and high-performance sets of standard cell libraries and memory compilers, all of which are available from TSMC and its IP ecosystem partners.

TSMC IP partners also offer interface IP cores supporting both mobile computing and HPC. IP cores such as LPDDR or MIPI PHYs are optimized for mobile solutions, whereas enterprise-dedicated DDR PHYs are optimized for HPC dedicated applications. Other IP cores, such as USB and PCIe PHYs support both segments. These 5nm IP cores are ready for design starts, and IP Silicon reports are available from TSMC and its partners.

The entire TSMC 5nm design infrastructure is available now from TSMC.