Toshiba showcased a 300mm wafer that had 128-Gbit NAND flash memory chips and was made by using 19nm process technology at "nano tech 2013 - The 12th International Nanotechnology Exhibition & Conference", the world's biggest exhibition of nanotechnology, that was held at the Tokyo Big Sight from January 30 to February 1. The company employed the 19nm process technology as well as a 3bit/cell multiple-level cell (MLC) technology. Compared to 2bit/cell MLC flash, the 3bit/cell MLC flash chips can be rewritten fewer times, meaning that the new flash is mostly suited for USB flash drives or flash cards, where absolute costs and density are the most important thing, and the performance and endurance are still adequate.

Toshiba claims that its 19nm process technology offers the same reliability as its previous 24nm process. The Japanese company used a structure that separates floating gates with air gaps to reduce the interference between memory cells.

Toshiba has been also working on the reduction of package thickness by stacking NAND chips in several layers. The company has managed to maintain a slim package for its 128-Gbyte memory by staking 16 layers of 30µm-thick 64-Gbit chips using a wire bonding technology.