Wednesday, March 21, 2018
Submit your own News for
inclusion in our Site.
Click here...
Breaking News
Qualcomm's New Snapdragon 845 Virtual Reality Development Kit Coming In Q2
South Korea Fines Facebook Over Unfair Practices
Futuremark Releases DirectX Raytracing Tech Demo
Samsung Expands its 8-Inch Foundry Offerings with New RF/IoT and Fingerprint Technology Solutions
Intel and Facebook Unveil Next Generation OCP Twin Lakes 1S Server
Facebook to Respond to FTC Questions Over Cambridge Analytica Case
AMD to Fix 13 processors Vulnerabilities Reported by CTS Labs Research
Microsoft Announces Project Denali SSD For Cloud-scale Applications
Active Discussions
Which of these DVD media are the best, most durable?
How to back up a PS2 DL game
Copy a protected DVD?
roxio issues with xp pro
Help make DVDInfoPro better with dvdinfomantis!!!
menu making
Optiarc AD-7260S review
cdrw trouble
 Home > News > General Computing > TSMC Ou...
Last 7 Days News : SU MO TU WE TH FR SA All News

Wednesday, October 02, 2013
TSMC Outlines Path To 16nm While Costs And Complexity Rise

Taiwan Semiconductor Manufacturing Co. on Tuesday outlined the progress made on its 20nm and 16nm nodes, although cost are higher than in the past.

Speaking at the TSMC 2013 Open Innovation Platform Exosystem Forum held in Silicon Valley, October 1st, 2013, TSMC's design ecosystem member companies (Cadence, Mentor Graphics, Synopsys, ARM and more) outlined TSMC's future design challenges and roadmaps.

TSMC said it has already taped out several 20nm chips and expects to let its customers start designing 16nm FinFET chips before the end of the year. By the end of 2014 it expects it will have taped out 25 20nm designs and also work on many 16nm chips.

TSMC's execs said that the company out 1.3 million eight-inch equivalent wafers each month, some of them now down to 20nm geometries.

The 20nm node is the first to use double patterning, requiring more masks and more runs under an immersion lithography machine. Future nodes at 10nm and beyond are expected to require triple or even quadruple patterning, raising costs again.

The 16nm node will be TSMC's first use of vertical transistors or FinFETs. This means that the 16nm node adds FinFETs to the existing 20nm process so it provides little gain in packing in more transistors per area of die. Onthe other hand, it offers benefits in lower power and higher performance.

TSMC's current customers for 20nm include Oracle, Xilinx, Altera and Qualcomm.

PS4 To Outsell Xbox One This Holiday Season: IDC        All News        DVD6C Files Lawsuit Against CDI Media
Samsung in Talks With BestBuy     General Computing News      3-D Drives Next-Generation NAND Flash

Get RSS feed Easy Print E-Mail this Message

Related News
TSMC Breaks Ground on 5nm Fab 18 in Southern Taiwan Science Park
TSMC Could Outpace Samsung in 7nm Volume Production This Year
TSMC to Invest $20bn in 3nm Chip Plant
Samsung Foundry in Advanced Discussions With New Customers for 7nm Chips
Apple Praises TSMC's Investments, Says iPhones Will be AI an Platform
TSMC Raises Forecasts for 2017 Due to 10nm Demand, Outlines 7 and 5nm Roadmap
TSMC Chairman Dr. Morris Chang to Retire
TSMC to Build 3nm Fab in Taiwan
Globalfoundries Asks EU to Probe TSMC
TSMC Updates its Roadmap, Talks About First 7nm Chips and EUV Migration
TSMC InFO packaging Enters Second Generation
TSMC Q2 Sales Slowed as Industry Expects the iPhone Launch

Most Popular News
Home | News | All News | Reviews | Articles | Guides | Download | Expert Area | Forum | Site Info
Site best viewed at 1024x768+ - CDRINFO.COM 1998-2018 - All rights reserved -
Privacy policy - Contact Us .