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Wednesday, October 02, 2013
TSMC Outlines Path To 16nm While Costs And Complexity Rise

Taiwan Semiconductor Manufacturing Co. on Tuesday outlined the progress made on its 20nm and 16nm nodes, although cost are higher than in the past.

Speaking at the TSMC 2013 Open Innovation Platform Exosystem Forum held in Silicon Valley, October 1st, 2013, TSMC's design ecosystem member companies (Cadence, Mentor Graphics, Synopsys, ARM and more) outlined TSMC's future design challenges and roadmaps.

TSMC said it has already taped out several 20nm chips and expects to let its customers start designing 16nm FinFET chips before the end of the year. By the end of 2014 it expects it will have taped out 25 20nm designs and also work on many 16nm chips.

TSMC's execs said that the company out 1.3 million eight-inch equivalent wafers each month, some of them now down to 20nm geometries.

The 20nm node is the first to use double patterning, requiring more masks and more runs under an immersion lithography machine. Future nodes at 10nm and beyond are expected to require triple or even quadruple patterning, raising costs again.

The 16nm node will be TSMC's first use of vertical transistors or FinFETs. This means that the 16nm node adds FinFETs to the existing 20nm process so it provides little gain in packing in more transistors per area of die. Onthe other hand, it offers benefits in lower power and higher performance.

TSMC's current customers for 20nm include Oracle, Xilinx, Altera and Qualcomm.

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