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Wednesday, March 29, 2017
Intel Details 10, 22nm Processes, Proposes Transistor-density Metric


Intel will start making 10nm chips this year it claims will lead the industry in transistor density using a reformulation of Moore's Law metrics, in an attempt to make up for lost time and a messy move to the 14-nm process.



Intel also announced a 22nm low-power FinFET node to compete for foundry business with fully depleted silicon-on-insulator (FD-SOI) from rivals such as Globalfoundries.

Intel's 10nm process will allow the company pack 100.8 million transistors per square millimeter. The company estimated 10nm foundry processes now in production from TSMC and Samsung have about half that density.

The first 10nm Cannonlake chips will be manufactured in the second half of this year, three years after Intel launched its 14nm process. It expects to continue a three-year cadence, stretching 10nm with two annual upgrades to be called 10+ and 10++.

Intel's 14++ sports higher performance than its initial 10nm process. However the 10nm node delivers lower power and higher density.

Intel's10nm node sports:

  • 34nm fin pitches
  • 53nm fin heights
  • 36nm minimum metal pitches
  • 272nm cell heights
  • 54nm gate pitches

Intel claimed the node sports the tightest gate and metal pitches in the industry and marks the industry's first use of self-align quad patterning. FinFETs are 25 percent taller and more closely packed than on its 14nm node.

After that the company will move to 7-nm, Stacy Smith, Intel's executive vice president leading manufacturing said there is "visibility" to the 5-nm process.

Intel is changing the way it measures process technology advancements, as the company wants continue to boast about hitting key Moore's Law metrics in terms of economics and the shrinking of chip sizes.

The company is actually changing the way it measures logic transistor density, using a wider cell width.

"Moore's Law is not dead, at least not for us," said Smith during an event to talk about manufacturing in San Francisco on Tuesday.

Moore's Law states that the cost of making chips goes down while the capabilities go up. Initially, Intel was doubling transistors every 18 months, which then expanded to two years. On its most recent 14-nanometer process, that time line expanded to three years.

Intel's metric averages density of a small and a large logic cell. Specifically, it uses a two-input NAND cell with two active gates and a scan flip-flop cell with as many as 25 active gates.

The existing metric of multiplying gate pitch and cell height gives a relative advance between nodes, rather than an absolute number of a node's capability.

With the new measurements, Intel will be able to boast that its manufacturing improvements are surpassing Moore's Law. The company also said it would cut the manufacturing cost per transistor by half with each new manufacturing process, which is in line with Moore's Law.

Rival fabs are now catching up with Intel. Samsung is making 10-nm chips for mobile devices such as Qualcomm's Snapdragon 835, though Intel says its latest 14-nm chips are as good as the 10-nm chips from Samsung and GlobalFoundries.

Intel will continue to deliver new PC and server chip architectures every year, with a minimum 15 percent performance improvement per generation. Coming next will be 8th Generation Core chips made on the 14-nm process, a fourth chip architecture on the process technology.

Intel has moved away from the once-famous "tick-tock" scaling, where new processes were "ticks" and new architectures were "tocks." It is switching to what the company calls "hyperscaling" advances, a new metaphor announced on Tuesday to describe manufacturing advances. Intel will now use the "+" and "++" symbols to mark advances in the 14-nm and 10-nm processes.

Intel is projecting 15 percent improvements in performance with each advance in the 10-nm + and ++ processes. Intel will also reduce the chip size to pack I/O, logic and SRAM blocks into a much smaller area.

Intel is also bringing the ability to mix and match different cores into an integrated system-on-chip. The cores could be made using different manufacturing processes. It's also much how ARM chips are designed and made, a process that integrates CPUs, modems, graphics processors and other cores into a single chip.

In addition, Intel will ramp its 22FFL node before the end of the year, targeting the same kinds of chips for mobile and the Internet of Things as FD-SOI from Globalfoundries and others. A 0.5 PDK is ready now and will be in a version 1.0 by June.

The process includes both high-performance transistors and low power ones with 100x less leakage than their peers in 28nm. It aims to compete with 28nm in costs by using simplified design rules and interconnects while using 14nm-like FinFETs.

The 22FFL process supports:

  • 45nm fin pitches,
  • 108nm gate pitches
  • 90nm metal pitches using single patterning
  • 630nm logic cell heights
  • 18.8 million transistors/mm2
  • 0.88mm2 SRAM bit cell

The gate and metal pitches are relaxed from Intel's first-generation FinFET 22nm node, which is at 90 and 80nm, respectively.

Finally, Intel provided more details on its current 14nm process, now in its third variant, 14++. Intel has made three generations of x86 processors in the node as well as its Stratix 10 FPGAs. By the end of the year it will be making its LTE modems in the process, too.

The Intel 14nm node uses:

  • 42nm Fin pitches
  • 52nm interconnect pitches
  • 70nm gate pitches
  • 399nm cell heights 399nm
  • 37.5 million transistors/mm2
  • 0.050mm2 SRAM cell


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