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Wednesday, October 18, 2017
Globalfoundries and Intel to Talk About 10, 7nm at IEDM

Intel and Globalfoundries will present papers on their 10nm and 7nm process nodes, respectively at the International Electron Devices Meeting (IEDM) in December.

Intel researchers will present a 10nm logic technology first unveiled in March. The platform features 3rd-generation FinFETs fabricated with self-aligned quadruple patterning (SAQP) for critical layers, leading to a 7nm fin width at a 34nm pitch, and a 46nm fin height; a 5th-generation high-k metal gate; and 7th-generation strained silicon. They will demonstrate its versatility by building a 204Mb SRAM having three different types of memory cells: a high-density 0.0312µm2 cell, a low voltage 0.0367µm2 cell, and a high-performance 0.0441µm2 cell.

There are 12 metal layers of interconnect, with cobalt dielectrics in the lowest two layers that yield a 5-10x improvement in electromigration and a 2x reduction in via resistance. NMOS and PMOS current is 71% and 35% greater, respectively, compared to 14nm FinFET transistors. Metal stacks with four or six workfunctions enable operation at different threshold voltages, and novel self-aligned gate contacts over active gates are employed.

Globalfoundries researchers will detail a fully integrated 7nm CMOS platform that provides significant density scaling and performance improvements over 14nm. It features a 3rd-generation FinFET architecture with self-aligned quadruple patterning (SAQP) used for fin formation, and self-aligned double patterning for metallization. The 7nm platform features an improvement of 2.8x in routed logic density, along with impressive performance/power responses versus 14nm: a >40% performance increase at a fixed power, or alternatively a power reduction of >55% at a fixed frequency. The researchers will demonstrate the platform by using it to build an incredibly small 0.0269µm2 SRAM cell. Multiple Cu/low-k BEOL stacks are possible for a range of system-on-chip (SoC) applications, and a unique multi-workfunction process makes possible a range of threshold voltages for diverse applications. A complete set of foundation and complex IP (intellectual property) is available in this CMOS platform for both high-performance computing and mobile applications.

During the IEDM 2017 event, which will be held on December 2-6, 2017 in San Francisco, many other companies will provide a view of research on the possible successors to the FinFET as a basic electronics switch.

Imec researchers will present at least three papers on the subject, including one on what it claims is the first circuit built with stacked silicon nanowires. The working ring oscillator used a new metallization process for n-type devices that led to greater control of threshold voltage.

In a separate paper, Imec will report performance characteristics of nanowires and nanosheets, arrays of the gate-all-around nanowires. Vertical test devices built in InGaAs showed Ion performance of 397µA/µm and peak transconductance of 1.6S/µm at Vds=0.5V.

Separately, Globalfoundries will describe a ring oscillator built with 14nm ferroelectric FinFETs. It ran at the same frequencies but lower power than similar devices in silicon. The doped hafnia structures have negative capacitance, so they could be used in commercial fabs, it said.

Macronix will report an advance in 3D NAND. 3D NAND memories typically are built from gate-all-around (GAA) devices arranged vertically, but it's difficult to precisely control their critical dimensions (CD) at high aspect ratios and so achieving ultra-high densities is problematic. Macronix researchers have already described a single-gate vertical channel (SGVC) 3D NAND, which makes use of arrays of vertically arranged single-gate, flat-cell thin film transistors with an ultra-thin body, which aren't as sensitive to CD variation as GAA devices. This year, they will describe how they used SGVC technology to build 128Gb (MLC)/192Gb (TLC) 3D NAND memories using just 16 layers, instead of the 48 layers that a GAA architecture would require. They say 48 layers could be used to build a 1Tb memory with the SGVC technology. The memories also demonstrated a robust immunity to read disturbances (>120M reads).

SK Hynix will share their work on ReRAM. The company will detail a selector made from a familiar and widely used material - SiO2, - doped with arsenic (As). It made possible a 25nm cross-point ReRAM of the 1S1R type (i.e., a one selector/one resistor architecture). The South Korean company claims that the ReRAM delivered the best performance ever reported at this geometry, with high current density (25 MA/cm2), fast on-/off-state transition times (52ns/23ns, respectively) and the ability to switch >105 cycles with high selectivity.

In addition, IBM and CEA-Leti will give separate talks on their work in monolithic 3D integration.

The University of Texas at Austin will discuss how they built a variety of two- and three-terminal graphene and MoS2 devices on paper. The graphene devices achieved a record 25 GHz cutoff frequency and performance remained high even when the paper was rolled into a two-inch diameter roll.

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