Intel will provide details about its Broadwell SoC, the 14nm SoC process, and potential Moore’s Law technologies such as gallium nitride and Tunneling Field Effect Transistors at the 2015 Symposia on VLSI Technology and Circuits this week in Kyoto, Japan. The company plans to present many papers that illustrate Intel’s pursuit of improved performance, density and energy efficiency in current and future process technologies, circuits and SoCs.

A session will describe a 14nm SoC platform technology based upon 2nd generation Tri-Gate transistor technology, which has been optimized for density, low power and wide dynamic range. 70nm gate pitch, 52nm metal pitch and 0.0499 mm2 HDC SRAM cells are the most aggressive design rules reported for 14/16 nm node SoC process to achieve Moore’s Law 2x density scaling over 22 nm node. High performance NMOS/PMOS drive currents of 1.3/1.2 mA/mm, respectively, have been achieved at 0.7 V and 100 nA/mm off-state leakage, 37%/50% improvement over 22 nm node. Ultra-low power NMOS/PMOS drives are 0.50/0.32 mA/mm at 0.7 V and 15pA/mm Ioff. This technology also deploys high voltage I/O transistors to support up to 3.3 V I/O. A full suite of analog, mixed-signal and RF features are also supported.

Computer chips need to reduce energy consumption. CMOS has dominated nearly 30 years of computing chip technology. Intel will descibe a new transistor technology called TFET (Tunneling Field Effect Transistor), which is a transistor research option that could improve energy efficient computation greater than 2X over CMOS. TFETs hold the promise of more environmentally-friendly data centers and mobile devices with longer battery life. The paper will discuss technical advances that may allow the TFET to realize low voltage logic and memory and overcome nanoscale manufacturing challenges.

Microprocessors built using advanced logic technologies can contain a billion or more transistors on each die. Ensuring that each of these transistors works as expected is one of the key challenges in technology development. A low operating voltage is critical to reducing power. Of all the device metrics, random variation of threshold voltage (Vt) in transistors plays a central role in determining the minimum operating voltage of products in a given process technology. Properly characterizing Vt random variation requires a large volume of measurements of minimum size devices to understand the rare event (high sigma) behavior. At the same time, a rapid measurement approach is required to keep the total measurement time practical. Intel will describe a new test structure and measurement approach that enables practical characterization of Vt distributions to high sigma and its application to Intel’s 14nm logic FinFET technology. The company will show that both NMOS and PMOS single fin devices have very low random Vt variation of 19mV and 24mV respectively, with a well-behaved normal distribution out to +/-5 sigma.

A diferent work investigates, for the first time, the use of GaN (gallium nitride) for realizing energy-efficient, compact voltage regulators and RF power amplifiers in low-power mobile SoCs. Intel fabricated a LG=90nm high-K dielectric enhancement-mode GaN transistor that showed low OFF-leakage, low ON-resistance, high drive current, and excellent power-added-efficiency at high RF output power density. These results provide significant improvements over industry-standard Si voltage regulator and GaAs RF power amplifier transistors, all at mobile SoC-compatible voltages. This work shows, for the first time, that the application space of GaN electronics can be expanded beyond the existing high-voltage power and RF electronics to include low-power mobile SoCs for improved battery life and user experience of mobile devices.

Evolving wireless communication standards and devices continue to push for high data rates and low power. This translates to higher ADC (analog to digital converter) speed requirements in receivers at lower power targets. An architecture known as SAR is promising for low-power ADCs, but its speed and resolution have been limited. An Intel paper presents a 12b 70MS/s sub-2 radix SAR ADC designed on Intel’s 14nm tri-gate CMOS process. The ADC incorporates a fully digital start-up calibration to correct capacitor mismatch errors to obtain high-resolution. The sub-2 radix architecture provides redundancy that improves speed. The comparator has a CMOS-input pre-amplifier with clamped-outputs to achieve low-noise and high-speed operation. This SAR ADC achieves 68.1dB SNDR at Nyquist, 70MS/s speed, consumes 4.3mW power, and occupies only 0.019mm2 area.

Dual-port embedded memories are utilized to provide high bandwidth and low-latency for high performance processor cores and graphics processing units on modern SoC designs. Intel will introduce a 14nm dual-port memory cell and array design featuring the smallest reported dual-port memory cell (0.094um2) and will discuss bitcell and design choices that enable low voltage operation for power efficient operation. The array demonstrates operation at supply voltages below 560mV and achieves 1GHz operation at 0.6V, utilizing a delayed keeper read assist circuit and several write assist circuit techniques. High density, high bandwidth embedded memories extend an advantage to SoC products, allowing a reduction in die area for high performance processors and GPU cores.

Intel Core M and 5th generation of Core processors (code named Broadwell) are fabricated on an optimized 14nm process technology resulting in a 49% reduction in feature-neutral die area. 14nm created a new optimized process flavor for Core M to improve energy efficiency for mobile devices. Techniques and optimizations were implemented to deliver 2.5x TDP reduction coupled with up to 60% higher graphics performance. New process technology combined with various design techniques reduced the minimum voltage of operation by 50 mV. Broadwell introduces the second generation of Fully Integrated Voltage Regulator (FIVR) with better droop control and parallel boot LVR (linear voltage regulator) mode added where-in rails are powered by LVR in deeper C-states to improve battery life . These features along with other power-reduction enhancements results in 35% reduction in active and standby power over first generation of FIVR. 3DL inductor technology, introduced for the first time in Broadwell, enables a 30% reduction in package thickness and improved low-load efficiency to increase battery life. IO re-partitioning of the SoC and a major re-design of DDR system resulted in a 30% reduction in I/O power. Shutting down various parts of the SoC die in various idle states (C* states) resulted in a 60% reduction in idle power. New software controlled co-optimization methods were implemented, such as duty-cycle control and dynamic display support, to improve the energy efficiency of the graphics and the display subsystem. Broadwell processor enhancements enable ≤9mm Fanless 2-in1’s for the first time on the Intel Core roadmap.