Intel and HP gave a public demonstration of the first dual-core Itanium processor, codenamed "montecito", at the International Supercomputer Conference (ISC) in Heidelberg, Germany. The new processor will be on the market later this year and will integrate 1.7 billion transistors, obviously addressed for the high-end server market. German website Heise Online reports that the benchmark demonstration held at ISC included a system which had four Montecito chips with eight physical cores clocked at 1.6 GHz. Sustained performance reached 45.8 GFlops and set a new record level for a 4-way system. A corrresponding Opteron system (four processor/eight cores) performs at 30 GFlop/s.

Intel's product roadmap includes another dual-core processor codenamed Montvalea, in 2006, and a quad-core Itanium processor with (Tukwila) in 2007/2008.

Tukwila will include an integerated Fully Buffered DIMM (FBD) memory controller. FB DIMM design resolves the limited memory performance of conventional registered DIMMs. Currently, the memory slot access rate per channel decreases as the memory bus speed increases, resulting in limited density build-up as channel speeds increase. The FB DIMM eliminates this "stub-bus" channel bottleneck by using point-to-point links that enable multiple memory modules to be connected serially to a given channel. This is expected to boost memory density and bandwidth to improve data processing in servers and workstations.

The Tukwila processor will also be compatible with the announced "Whitefield" Xeon processor.