Cadence Announces Tapeout of 14 nm Test-Chip
Cadence announced today the tapeout of a 14-nanometer test-chip featuring an ARM Cortex-M0 processor implemented using IBM's FinFET process technology. The 14-nanometer ecosystem and chip...
Cadence Releases First 28nm DDR4 Design IP Solutions
Cadence Design Systems has announced that the first products in its DDR4 SDRAM PHY and memory controller design intellectual property (IP) family have been proven...
Samsung and Cadence Production of 32nm HD Digital Camera SoC for Ambarella
Samsung and Cadence announced today the initial production of Ambarella's 32-nanometer (nm) HD digital camera system-on-chip (SoC) at ARM TechCon 2011. This SoC, in production...
Cadence and TSMC to Deliver DFM Services for TSMC Advanced Processes
Cadence Design Systems, Inc. has collaborated with TSMC to deliver their customers DFM expertise and technology in a service model. In an effort to reduce...
Toshiba Adopts Cadence Solution for 65nm Design
Cadence Design Systems announced that Toshiba has adopted Cadence QRC Extraction for its most advanced 65nm design flows. Cadence QRC Extraction provides silicon-accurate parasitic extraction...
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