Samsung and Cadence Production of 32nm HD Digital Camera SoC for Ambarella
Samsung and Cadence announced today the initial production of Ambarella's 32-nanometer (nm) HD digital camera system-on-chip (SoC) at ARM TechCon 2011.
This SoC, in production at the S1-Line at Samsung's Giheung facility, was built
using 32nm gate-first High-k Metal Gate (HKMG) process technology from Samsung
Electronics' foundry business, Samsung Foundry, a complete Cadence digital design
flow including the Encounter and Incisive platforms and ARM Cortex processor and
Artisan physical IP. The new Ambarella A7L SoC promises to bring new levels of
performance and power savings to digital lifestyle HD camera applications.
"Impressively, Samsung Foundry's process technology, combined with the Cadence digital flow, enabled us to hit our aggressive performance targets while achieving 95 percent power savings during power shutoff mode and 60 percent average power savings over operation and sleep modes," said Chan Lee, vice president of VLSI, Ambarella, Inc.
The Ambarella A7L SoC design included several million logic gates and scores of Ambarella's custom proprietary high speed mixed signal blocks. Ambarella also utilized Samsung Foundry's full turn-key offering, including manufacturing, test and packaging, to accelerate time to market and simplify the supply chain.
The Ambarella A7L design took advantage of the complete digital flow from Cadence for IP integration and validation. Engineers were able to meet and exceed their aggressive performance and power design objectives using key capabilities such as intelligent power shutoff and sleep modes. The integrated design flow included the Encounter Digital Implementation System, featuring the NanoRoute Router for 32nm digital routing, Encounter RTL Compiler, Encounter Timing System, Encounter Power System, and Incisive Enterprise Simulator, covering all elements of design, verification and implementation.
In advance of this project Samsung Foundry assisted in porting all necessary Ambarella IP to its production-ready 32nm HKMG process technology to ensure that the Ambarella proprietary IP was pre-verified in the new node. Samsung Foundry also provided silicon-proven ARM Artisan optimized logic and memory IP in support of the overall IP needed for this project.
"Impressively, Samsung Foundry's process technology, combined with the Cadence digital flow, enabled us to hit our aggressive performance targets while achieving 95 percent power savings during power shutoff mode and 60 percent average power savings over operation and sleep modes," said Chan Lee, vice president of VLSI, Ambarella, Inc.
The Ambarella A7L SoC design included several million logic gates and scores of Ambarella's custom proprietary high speed mixed signal blocks. Ambarella also utilized Samsung Foundry's full turn-key offering, including manufacturing, test and packaging, to accelerate time to market and simplify the supply chain.
The Ambarella A7L design took advantage of the complete digital flow from Cadence for IP integration and validation. Engineers were able to meet and exceed their aggressive performance and power design objectives using key capabilities such as intelligent power shutoff and sleep modes. The integrated design flow included the Encounter Digital Implementation System, featuring the NanoRoute Router for 32nm digital routing, Encounter RTL Compiler, Encounter Timing System, Encounter Power System, and Incisive Enterprise Simulator, covering all elements of design, verification and implementation.
In advance of this project Samsung Foundry assisted in porting all necessary Ambarella IP to its production-ready 32nm HKMG process technology to ensure that the Ambarella proprietary IP was pre-verified in the new node. Samsung Foundry also provided silicon-proven ARM Artisan optimized logic and memory IP in support of the overall IP needed for this project.
