"DDR4 is going to be the next big thing in DRAMs, but its signaling is challenging to handle," said Jim Handy of Objective Analysis. "As PCs migrate to DDR4 DRAMs, this standard will become the volume leader, giving it a price advantage that will be impossible to ignore. ASIC designers who want to take advantage of that pricing are likely to need a lot of help putting a reliable interface on their products."
The Cadence PHY family includes a high-speed implementation of the DDR4 PHY that exceeds the data rates specified in the DDR-2400 specifications draft, while offering interoperability with current DDR3 and DDR3L standards. Also proven in TSMC 28HPM silicon, is a low-power, all-digital mobile PHY implementation that exceeds the data rates called for in both the DDR-1600 and DDR-1866 DDR3 standards and the maximum data rate of the low-power LPDDR2 standard.