Synopsys, Inc. announced certification of its digital and custom design platforms for TSMC's N6 and N5 process technologies.
Synopsys' collaboration with TSMC has resulted in accelerating next-generation product design for vertical markets, including high-performance computing (HPC), mobile, 5G, and AI chip designs.
Synopsys' collaboration with TSMC also extends to 3DIC process technologies, which include CoWoS, InFO, and TSMC-SoIC that enable scalable integration for achieving greater functionality and enhanced system performance.
Synopsys design tools for HPC and mobile design flows enable designers to take full advantage of TSMC's N6 and N5 process technologies that enhance density, operating frequency, and power consumption. Tools also have been improved to support ultra-low VDD requirements for low power consumption mobile and 5G designs. As part of the design flow platform certification, results from Synopsys StarRC and PrimeTime® signoff solutions were compared to implementation results. PrimeTime timing reports were also well compared to the golden HSPICE results, to successfully achieve design flow correlation targets that will improve design convergence and shorten overall time-to-market.
Cadence releases 56G Long-Reach PAM4 SerDes on TSMC N7 and N6 Processes
In related news, Cadence Design Systems, Inc. today announced the availability of 56G long-reach SerDes IP on TSMC’s N7 and N6 process technologies. Hyperscale computing continues to be the main driver for very high-speed SerDes, and 112G/56G is a key enabler for cloud data center and optical networking applications. 56G connectivity is particularly important for 5G infrastructure deployment, both in baseband and remote radio head systems. To address this market, Cadence has expanded its PAM4 SerDes portfolio with 56G long-reach SerDes IP on the TSMC N7 and N6 processes delivering optimized power, performance and area (PPA).
The Cadence 56G long-reach SerDes IP delivers a number of benefits, including:
- 36db+ insertion loss using Cadence’s multi-rate DSP technology
- Industrial temperature range, CPRI data rate support and per-lane PLL are ideal for 5G applications
- 56G long-reach performance has been achieved on N7 test silicon and is compatible with the N6 process
- Fully compliant with the IEEE standard specification
- Programmable power configurations via a unique firmware-controlled adaptive power optimizer, which provides optimal power and performance tradeoffs and more efficient system designs based on platform requirements
- Optimal data recovery through the programmable DSP-based architecture, which allows optimal power delivery for a given reach and provides data recovery under lossy and noisy channel conditions
- Improved flexibility enabled by the extended reach capability lets customers use lower cost PCBs and achieve greater flexibility in PCB and system design