NEC Introduces First Ultra-Low-Power 55-nanometer Embedded DRAM Technology
NEC Electronics Corporation today announced the industry's first 55- nanometer (nm) CMOS-compatible embedded DRAM (eDRAM) technology, UX7LSeD.
An enhancement to NEC Electronics' patented metal-insulator-metal (MIM2) technology, the new eDRAM process is the industry's first combination of hafnium silicate film and nickel silicide, which has resulted in reduced power consumption and leakage current at this advanced node. Optimized for high-speed, low-power operation, the new process can be applied to system-on-chip (SOC) devices designed for a broad range of products—from mobile equipment such as cell phones and mobile handheld devices to digital consumer devices such as gaming consoles.
The introduction of hafnium silicate film to the embedded DRAM process has allowed NEC Electronics to reduce leakage current while increasing on-current by as much as 20 percent. Reducing the leakage current is an important factor to maintaining reasonable data retention time in eDRAM macros. The new manufacturing material also has allowed NEC Electronics to continue to use polysilicon gates, as opposed to metal gates, which helps to reduce process risks for volume production.
The use of nickel silicide, a material suitable for aggressively scaled structures, helps to maintain low parasitic resistance of the scaled-down eDRAM cell and peripheral circuits and also reduce standby and operating power. Furthermore, the high dielectric constant (high-k) technology applied to the eDRAM cell transistor boosts its performance, reduces leakages and suppresses variability, as the work-function modulation effect of high-k is fully exploited to reduce transistor channel concentration.
These new materials and the proprietary MIM2 technology are enabling NEC Electronics to deliver eDRAM solutions with smaller cell sizes, higher memory integration, ample storage capacitance and lower cell heights, and all the while maintain the merits of existing eDRAM technology, such as CMOS compatibility, low power and high-speed random access.
NEC Electronics' eDRAM Technology Benefits
NEC Electronics' eDRAM combines DRAM density with SRAM-like performance, low latency and robust performance. With lower power consumption and a lower soft error rate than embedded SRAM, NEC Electronics' eDRAM has blocks that can be rotated in any orientation on a chip to simplify integration with other on-chip components while preserving the performance and power consumption benefits afforded by NEC Electronics' process. The upper metal layers of an ASIC also can be routed over the top of eDRAM blocks to simplify chip design, improve timing and conserve silicon.
The NEC Electronics process employs both a cylindrical-type stacked capacitor structure that ensures high yields and a low-temperature MIM2 capacitor that accelerates performance. The MIM2 technology uses zirconium oxide (ZrO2), a dielectric material with a high-k factor that allows the embedded DRAM's smaller bit cells to retain storage capacitance. Unlike its commodity DRAM process, NEC Electronics' eDRAM process uses the same structure as its standard CMOS process, and thus is fully compatible with it. This compatibility dramatically reduces turnaround time by minimizing the number of process steps needed to add eDRAM.
NEC Electronics' 55 nm 8-megabit (Mb) and larger embedded DRAM macros are expected to be available for volume production in the second half of 2007.
The introduction of hafnium silicate film to the embedded DRAM process has allowed NEC Electronics to reduce leakage current while increasing on-current by as much as 20 percent. Reducing the leakage current is an important factor to maintaining reasonable data retention time in eDRAM macros. The new manufacturing material also has allowed NEC Electronics to continue to use polysilicon gates, as opposed to metal gates, which helps to reduce process risks for volume production.
The use of nickel silicide, a material suitable for aggressively scaled structures, helps to maintain low parasitic resistance of the scaled-down eDRAM cell and peripheral circuits and also reduce standby and operating power. Furthermore, the high dielectric constant (high-k) technology applied to the eDRAM cell transistor boosts its performance, reduces leakages and suppresses variability, as the work-function modulation effect of high-k is fully exploited to reduce transistor channel concentration.
These new materials and the proprietary MIM2 technology are enabling NEC Electronics to deliver eDRAM solutions with smaller cell sizes, higher memory integration, ample storage capacitance and lower cell heights, and all the while maintain the merits of existing eDRAM technology, such as CMOS compatibility, low power and high-speed random access.
NEC Electronics' eDRAM Technology Benefits
NEC Electronics' eDRAM combines DRAM density with SRAM-like performance, low latency and robust performance. With lower power consumption and a lower soft error rate than embedded SRAM, NEC Electronics' eDRAM has blocks that can be rotated in any orientation on a chip to simplify integration with other on-chip components while preserving the performance and power consumption benefits afforded by NEC Electronics' process. The upper metal layers of an ASIC also can be routed over the top of eDRAM blocks to simplify chip design, improve timing and conserve silicon.
The NEC Electronics process employs both a cylindrical-type stacked capacitor structure that ensures high yields and a low-temperature MIM2 capacitor that accelerates performance. The MIM2 technology uses zirconium oxide (ZrO2), a dielectric material with a high-k factor that allows the embedded DRAM's smaller bit cells to retain storage capacitance. Unlike its commodity DRAM process, NEC Electronics' eDRAM process uses the same structure as its standard CMOS process, and thus is fully compatible with it. This compatibility dramatically reduces turnaround time by minimizing the number of process steps needed to add eDRAM.
NEC Electronics' 55 nm 8-megabit (Mb) and larger embedded DRAM macros are expected to be available for volume production in the second half of 2007.
