The researchers also optimized the insulating tunnel oxide and inter-poly dielectric of the cell, as well as the surrounding dielectric, to minimize leakage and trapping, resulting in performance similar to previous generations.
Taiwan-based TSMC will also unveil a complete high-performance 22/20nm CMOS logic technology at IEDM 2010. It features FinFET transistor architectures, aggressive 193nm immersion lithography, SiGe stressors, metal gates and high-k dielectrics. The FinFETs, built with dual-epitaxy and multiple stressors, demonstrate outstanding performance in both n- and p-channel versions, enabling maximum design flexibility, according to TSMC's researchers. N-/P-channel on-current is 1200/1100μA/μm respectively, while off-current for both N and P versions is 100nA/μm. The researchers used the new technology to build a dense 0.1μm2 SRAM memory cell, which had excellent noise characteristics (90mV noise margin) even at a low 0.45V operating voltage.