AMD Describes Upcoming Fusion Processor at ISSCC 2010
AMD announced the "Llano", the company's first chip that packs both a CPU and a GPU parts, part of AMD's upcoming Fusion series of chips.
Actually AMD calls the Liano chip as an "application processor unit," or APU. It combines a full DX11-compatible GPU with four CPU cores on a single, 32nm processor die.
AMD said that the first samples of the Llano chips will be available to customers in the first half of this year. It will be manufactured by GlobalFoundries' 32nm SOI High-K metal gate process and 2nd generation immersion lithography. Siliccon Germanium-based strained-sillicon is used to improve peformance.
The Liano chip consists of two parts. The first opart is four x86 CPU cores. The size of its core is just 9.69mm2, while the chip integrates a total of more than 35 million transistors. The advanced 32nm sillicon has also a significant impact on the power consumption of the chip, which will range from 2.5W to 25W. Operation frequencies are expected to be beyond 3GHz, powered by voltages of 0.8-1.3V. In addition, each of these 4 cores has a 1MB of DDR3 of memory cache.
The Llano chips are expected to directly compete with Intel's 'Sandy Bridge' 32nm chips, which will also integrate graphics but only for Direct X 10. Intel plans to release the chips in 2011. Llano is also possible to compete with NVIDIA's upcoming x86 CPU + GPU combination.
AMD announced the Llano chips at the International Solid State Circuits Conference ISSCC 2010 held in San Francisco, CA.
Without diving too deep into the technical details, AMD has applied the folowing innovations to Liano:
- Core power gating - a feature of the processor that disconnects power to the core when it's not in use, helping to reduce overall power consumption and extend battery life. AMD's SOI process allows us to use more efficient NFET transistors for power gating as opposed to the PFET transistors used with a bulk silicon manufacturing process. In addition, AMD uses the actual chip package to re-distribute the gated ground rather than an additional thick metal layer used by other gating schemes. In total, this equates to a greater than 90% estimated reduction in leakage power.
- Digital APM Module - Measuring core power consumption is extremely important for a processor to understand how hot it?s running and when performance can be increased within a thermal constraint. There are two schools of thought here: measure temperature and amps via analog methods, or measure power consumption digitally. The former is subject to a variety of environmental issues (temperature in the room, dust on the fan, etc.), while the latter is more accurate and repeatable. AMD has implemented a digital power management technique that allows us to measure power consumption more accurately, thus helping to optimize performance-per-watt in real-time.
- De-Populated Clock Grid - Clock gating is a technique where the clock signal is combined with a control signal to either enable or disable the clock for certain parts of the circuit. This helps save power by effectively shutting down portions of a digital circuit when they are not in use and is used extensively in AMD's x86 core. An effective way to get this clock signal to every part of a chip that needs it, with the lowest skew, is a metal grid. In a large microprocessor, the power used to drive the clock signal can be over 30% of the total power used by the entire chip. We've been able to dramatically reduce the amount of metal and buffering in this system to reduce clock switching power by an estimated factor of 2.
AMD said that the first samples of the Llano chips will be available to customers in the first half of this year. It will be manufactured by GlobalFoundries' 32nm SOI High-K metal gate process and 2nd generation immersion lithography. Siliccon Germanium-based strained-sillicon is used to improve peformance.
The Liano chip consists of two parts. The first opart is four x86 CPU cores. The size of its core is just 9.69mm2, while the chip integrates a total of more than 35 million transistors. The advanced 32nm sillicon has also a significant impact on the power consumption of the chip, which will range from 2.5W to 25W. Operation frequencies are expected to be beyond 3GHz, powered by voltages of 0.8-1.3V. In addition, each of these 4 cores has a 1MB of DDR3 of memory cache.
The Llano chips are expected to directly compete with Intel's 'Sandy Bridge' 32nm chips, which will also integrate graphics but only for Direct X 10. Intel plans to release the chips in 2011. Llano is also possible to compete with NVIDIA's upcoming x86 CPU + GPU combination.
AMD announced the Llano chips at the International Solid State Circuits Conference ISSCC 2010 held in San Francisco, CA.
Without diving too deep into the technical details, AMD has applied the folowing innovations to Liano:
- Core power gating - a feature of the processor that disconnects power to the core when it's not in use, helping to reduce overall power consumption and extend battery life. AMD's SOI process allows us to use more efficient NFET transistors for power gating as opposed to the PFET transistors used with a bulk silicon manufacturing process. In addition, AMD uses the actual chip package to re-distribute the gated ground rather than an additional thick metal layer used by other gating schemes. In total, this equates to a greater than 90% estimated reduction in leakage power.
- Digital APM Module - Measuring core power consumption is extremely important for a processor to understand how hot it?s running and when performance can be increased within a thermal constraint. There are two schools of thought here: measure temperature and amps via analog methods, or measure power consumption digitally. The former is subject to a variety of environmental issues (temperature in the room, dust on the fan, etc.), while the latter is more accurate and repeatable. AMD has implemented a digital power management technique that allows us to measure power consumption more accurately, thus helping to optimize performance-per-watt in real-time.
- De-Populated Clock Grid - Clock gating is a technique where the clock signal is combined with a control signal to either enable or disable the clock for certain parts of the circuit. This helps save power by effectively shutting down portions of a digital circuit when they are not in use and is used extensively in AMD's x86 core. An effective way to get this clock signal to every part of a chip that needs it, with the lowest skew, is a metal grid. In a large microprocessor, the power used to drive the clock signal can be over 30% of the total power used by the entire chip. We've been able to dramatically reduce the amount of metal and buffering in this system to reduce clock switching power by an estimated factor of 2.
