ATI Joins the X Initiative
ATI, Cadence Design Systems and Taiwan Semiconductor Manufacturing Company (TSMC) have successfully produced the X Architecture device.
The ATI chip is a high-performance, high-volume PCI-Express graphics processor designed for desktop and notebook computers. The X Architecture is a new approach to chip design whereby diagonal interconnects are employed to reduce chip costs, increase performance and lower power consumption.
The ATI device was implemented using the Cadence X Architecture design solution and manufactured using TSMC's 0.11-micron process. This implementation eliminated one metal layer from the original Manhattan design, reducing die costs. The new device is expected to enter volume production late in the year.
"The X Architecture opens up a host of new possibilities for innovation in chip design," said Greg Buchner, vice president of Engineering at ATI. "As the industry leader in advanced graphics and digital media processors, ATI has long been a pioneer in adopting new chip design technologies. Using the Cadence X Architecture design solution, we have been able to increase the performance envelope while reducing costs, providing new opportunities and possibilities within our PC and consumer businesses."
The Cadence X Architecture design solution enables the pervasive use of diagonal routes and employs the familiar netlist-to-GDSII flow. While leveraging Cadence's industry-proven expertise in the Manhattan implementation, the solution draws on innovations in placement, routing, infrastructure and extraction technologies. Cadence X Architecture design solutions for TSMC's 0.13-micron and 0.11-micron process nodes are now available to select customers under Cadence's value-based business model.
To bring the X Architecture into manufacturing reality, TSMC created extensive test structures to formulate competitive X Architecture design rules and developed a unique OPC model and mask making techniques. TSMC also created enhanced technology files to handle diagonal design rules and parasitic extraction.
ATI is joining the X Initiative, and becomes the first fabless chip design member company.
"We're elated to welcome ATI, the world's leading graphics chip maker, as the first fabless member of the X Initiative," said Aki Fujimura, X Initiative steering group member, the co-inventor of X Architecture and chief technology officer, New Business Incubation, at Cadence. "The fabrication of ATI's chip by TSMC caps our efforts to ready the global semiconductor supply chain for production of fabless chips using the X Architecture."
About the X Architecture
The X Architecture, the first production-worthy approach to the pervasive use of diagonal interconnect, reduces the total interconnect, or wiring, on a chip by up to 20 percent and via-counts by up to 30 percent, resulting in significant improvements in chip area, performance, power and cost. For the past 20 years, chip design has been primarily based on the de facto industry standard "Manhattan" architecture, named for its right-angle interconnects resembling a city-street grid. The X Architecture rotates the primary direction of the interconnect in the fourth and fifth metal layers by 45 degrees from a Manhattan architecture. The new architecture maintains compatibility with existing cell libraries, memory cells, compilers and IP cores by preserving the Manhattan geometry of metal layers one through three. For more information on the X Architecture technology visit www.xinitiative.org.
The ATI device was implemented using the Cadence X Architecture design solution and manufactured using TSMC's 0.11-micron process. This implementation eliminated one metal layer from the original Manhattan design, reducing die costs. The new device is expected to enter volume production late in the year.
"The X Architecture opens up a host of new possibilities for innovation in chip design," said Greg Buchner, vice president of Engineering at ATI. "As the industry leader in advanced graphics and digital media processors, ATI has long been a pioneer in adopting new chip design technologies. Using the Cadence X Architecture design solution, we have been able to increase the performance envelope while reducing costs, providing new opportunities and possibilities within our PC and consumer businesses."
The Cadence X Architecture design solution enables the pervasive use of diagonal routes and employs the familiar netlist-to-GDSII flow. While leveraging Cadence's industry-proven expertise in the Manhattan implementation, the solution draws on innovations in placement, routing, infrastructure and extraction technologies. Cadence X Architecture design solutions for TSMC's 0.13-micron and 0.11-micron process nodes are now available to select customers under Cadence's value-based business model.
To bring the X Architecture into manufacturing reality, TSMC created extensive test structures to formulate competitive X Architecture design rules and developed a unique OPC model and mask making techniques. TSMC also created enhanced technology files to handle diagonal design rules and parasitic extraction.
ATI is joining the X Initiative, and becomes the first fabless chip design member company.
"We're elated to welcome ATI, the world's leading graphics chip maker, as the first fabless member of the X Initiative," said Aki Fujimura, X Initiative steering group member, the co-inventor of X Architecture and chief technology officer, New Business Incubation, at Cadence. "The fabrication of ATI's chip by TSMC caps our efforts to ready the global semiconductor supply chain for production of fabless chips using the X Architecture."
About the X Architecture
The X Architecture, the first production-worthy approach to the pervasive use of diagonal interconnect, reduces the total interconnect, or wiring, on a chip by up to 20 percent and via-counts by up to 30 percent, resulting in significant improvements in chip area, performance, power and cost. For the past 20 years, chip design has been primarily based on the de facto industry standard "Manhattan" architecture, named for its right-angle interconnects resembling a city-street grid. The X Architecture rotates the primary direction of the interconnect in the fourth and fifth metal layers by 45 degrees from a Manhattan architecture. The new architecture maintains compatibility with existing cell libraries, memory cells, compilers and IP cores by preserving the Manhattan geometry of metal layers one through three. For more information on the X Architecture technology visit www.xinitiative.org.
