Intel And ITRI Develop Super-speed Experimental Memory
Intel Labs announced Tuesday an experimental low-power but high-performance memory array jointly developed with Taiwan's Industrial Technology Research Institute (ITRI).
Designed for future ultra-mobile devices such as ultrabook lightweight computers, tablet computers and smartphones, the new memory architercture is the result of a partnership announced last year between Intel Labs and the Industrial Technology Research Institute(ITRI) of Taiwan to establish the Intel and ITRI Research Collaboration (IIRC).
The quicksilver experimental memory array is an energy-efficient memory architecture which can achieve longer battery life, faster integration of mobile data, better graphics functions and a better user experience on mobile devices, Intel CTO Justin Rattner said, according to a report by the Central News Agency (CNA). The array is helpful for boosting development of 3D stack IC and system optimization technology.
The research is expected to begin testing on devices in 2013, including handheld devices and super computers , Rattner said.
Progress in 14nm technology
Besides the announcement for the new memory architecture, Intel CTO Justin Rattner on December 4 said that Intel's development of 14nm technology is on schedule with volume production to kick off in 2014. In addition, he added that the development of 18-inch wafers was also under way through cooperation with Intel's partners and are expected to start entering production in 2017.
Rattner said that Intel's agressive technology advancement will allow Moore's Law to extend for another 10 years.
Intel plans to enter 10nm, 7nm and 5nm process generations starting 2015.
Samsung is also set to enter 20nm in 2013 and is already working on its 14nm node, while TSMC's 20nm process will enter small volume production in the second half of 2013. Globalfoundries has announced its 14nm FinFET process will start pilot production at the end of 2013 and enter mass production in 2014.
The quicksilver experimental memory array is an energy-efficient memory architecture which can achieve longer battery life, faster integration of mobile data, better graphics functions and a better user experience on mobile devices, Intel CTO Justin Rattner said, according to a report by the Central News Agency (CNA). The array is helpful for boosting development of 3D stack IC and system optimization technology.
The research is expected to begin testing on devices in 2013, including handheld devices and super computers , Rattner said.
Progress in 14nm technology
Besides the announcement for the new memory architecture, Intel CTO Justin Rattner on December 4 said that Intel's development of 14nm technology is on schedule with volume production to kick off in 2014. In addition, he added that the development of 18-inch wafers was also under way through cooperation with Intel's partners and are expected to start entering production in 2017.
Rattner said that Intel's agressive technology advancement will allow Moore's Law to extend for another 10 years.
Intel plans to enter 10nm, 7nm and 5nm process generations starting 2015.
Samsung is also set to enter 20nm in 2013 and is already working on its 14nm node, while TSMC's 20nm process will enter small volume production in the second half of 2013. Globalfoundries has announced its 14nm FinFET process will start pilot production at the end of 2013 and enter mass production in 2014.
