Toshiba has developed the world’s lowest power consumption radio receiver architecture that meets Bluetooth Low Energy (BLE) standards. The Japanese company has also developed a 4-Mb-class memory circuit using STT-MRAM for processors and system-on-a-chips (integrated memory.) Wireless Receiver Architecture for Bluetooth Low Energy

Toshiba says it has managed to reduce the power consumption of the newly developed Bluetooth Low Energy (BLE) radio receiver by reducing the number of components in its electrical circuits.

The data collected from wearable devices are commonly transmitted to an external device such as a smartphone by BLE. This has generated a demand for wearable devices that have small size, light weight, and long battery life.

This new receiver architecture features data demodulation using an analog signal processor with a single in-phase component, rather than a conventional two-signal analog signal processor that has both in-phase and orthogonal components. This was achieved by setting the frequency of the frequency synthesizer of the receiver circuit.

Another feature of this architecture is that it eliminates the need for an A/D converter in demodulation processing. This was achieved by configuring the receiver to use a digital frequency synthesizer. Toshiba's engineers have developed a demodulation configuration that allows A/D conversion of the signal by means of the digital frequency synthesizer alone, utilizing its noise reduction function.
According to their calculations, the new receiving architecture achieves a 10% reduction in power consumption compared with current devices with a BLE-compatible analog circuit receiver by both reducing the number of circuit blocks and eliminating the A/D converter altogether.

Toshiba will present this technology in San Francisco on February 3 at the 2016 IEEE International Solid-State Circuits Conference (ISSCC).

Cache Memory with the High Power Performance Using STT-MRAM Magnetic Memory

Toshiba, in cooperation with the research group of Professor Hiroshi Nakamura from the Faculty of Engineering at Tokyo University, has
developed a 4-Mb-class memory circuit using STT-MRAM, a new type of magnetic memory that integrates 65-nm silicon transistors, for high-performance processors and use in system-on-a-chip (SoC)

This memory circuit offers 3.3ns memory access, which is fast enough for use as cache memory, and consumes less than 1/10th of the energy that conventional integrated memory (SRAM: static random-access memory) does.

In terms of the power consumption in semiconductor chips, reducing the power consumption of the memory block has become a focus of development as the size of SRAM inside the chips has increased. In particular, the power consumption attributable to current leaking inside the memory (leakage current) is large, and Toshiba has been continuing to develop magnetic tunneling junction (MTJ) non-volatile magnetic memory that offers high speed and low power consumption, with the expectation that there will be a change from the currently used volatile memory to non-volatile memory.

However, since power consumption due to memory writes and memory control circuits (peripheral circuits) is high, the overall power consumption is not low enough for use in cache memory, even for a memory array circuit that is implemented with lower power consumption.

In order to solve the current-related problems, Toshiba has developed circuits capable of high-speed power shutdown-and–recovery, at sub 100-ns speeds, to allow the memory-control circuit unit to more fully achieve a normally off state, and we have made improvements that allow the power supply to be cut off at high speed in units not required to operate, according to the memory operation state. Furthermore, in order to shut down the power supply efficiently, researchers at Tokyo University developed an algorithm that monitors the patterns of memory access and predicts the access pattern that is highly probably to be next. This algorithm is built into the memory-control circuit. By using these technologies, ther esearchers have been able to reduce the power consumption to less than 1/10th that of SRAM.

The technology will be also presented at the 2016 IEEE International Solid-State Circuits Conference (ISSCC).

New 3D NAND Semiconductor Production Facility

Moving beyond new technologies, Toshiba has also announced that it is gearing up for future expanded production of "BiCS FLASH", its proprietary 3D flash memory, by acquiring 150,000m2 of land adjacent to its Yokkaichi Operations memory production complex in Mie prefecture. The land borders the eastern and northern parts of the complex, and will cost approximately 3 billion yen.

The new site is expected to be ready for construction by March 2017.

Production of BiCS FLASH requires a new cleanroom with dedicated equipment for the 3D process. The New Fab 2 building, which will be fully completed in the first half of FY2016, will initially provide this space.

Toshiba positions the memory business as a core business, and will continue to make focused investments that enhance its market competitiveness.