TSMC Tapes out First 5nm Chip, Outlines Packaging Techniques
TSMC has taped out its first chip in a process that partially makes use of extreme ultraviolet lithography (EUV) and will start risk production in...
Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies
Cadence digital, signoff and custom/analog tools have achieved the latest DRM and SPICE certifications for TSMC 5nm and 7nm+ FinFET process technologies for mobile and...
Samsung Talks About Process Technology Roadmap, Down to 3-nanometer Using GAA
The Samsung Foundry Forum 2018 Japan was held in Tokyo and Samsung disclosed details about its silicon innovations that will be at the heart of...
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