IBM Develops Chip-stacking Technique
IBM said on Wednesday it will be able to make microchips faster and more energy efficient by stacking components on top of each other, a breakthrough that cuts the distance an electrical signal needs to travel.
The technique works by drilling tiny holes through a wafer of silicon and filling them with metal. Components such as memory can then be stacked on top of the main part of the chip, eliminating the need for wires stretching out to the sides.
IBM likened the method to replacing a sprawling airport parking lot with a multi-storied garage right next to the terminal. Like people walking from the garage to the terminal, electrical signals do not have to travel as far in a chip with stacked components.
"It opens up a range of applications and neat things we can do," said Lisa Su, head of semiconductor research at IBM.
IBM will use the method to make power management chips for wireless devices later this year, allowing them to use 40 percent less power than previous versions, according to IBM.
Eventually, IBM plans to incorporate the technique into full-blown processors.
IBM said that the new technique will extend Moore?s Law beyond its expected limits.
It is the latest achievement by IBM's semiconductor researchers, who have in recent months hit upon several breakthroughs in materials science and chip design. In December, IBM announced the first 45nm chips using immersion lithography and ultra-low-K interconnect dielectrics.
In January, IBM announced "high-k metal gate," which substitutes a new material into a critical portion of the transistor that controls its primary on/off switching function. The material provides superior electrical properties, while allowing the size of the transistor to be shrunk beyond limits being reached today.
In February,IBM revealed a first-of-its-kind, on-chip memory technology that features the fastest access times ever recorded in eDRAM (embedded dynamic random access memory).
Then in March, IBM unveiled a prototype optical transceiver chipset capable of reaching speeds at least eight-times faster than optical components available today.
IBM likened the method to replacing a sprawling airport parking lot with a multi-storied garage right next to the terminal. Like people walking from the garage to the terminal, electrical signals do not have to travel as far in a chip with stacked components.
"It opens up a range of applications and neat things we can do," said Lisa Su, head of semiconductor research at IBM.
IBM will use the method to make power management chips for wireless devices later this year, allowing them to use 40 percent less power than previous versions, according to IBM.
Eventually, IBM plans to incorporate the technique into full-blown processors.
IBM said that the new technique will extend Moore?s Law beyond its expected limits.
It is the latest achievement by IBM's semiconductor researchers, who have in recent months hit upon several breakthroughs in materials science and chip design. In December, IBM announced the first 45nm chips using immersion lithography and ultra-low-K interconnect dielectrics.
In January, IBM announced "high-k metal gate," which substitutes a new material into a critical portion of the transistor that controls its primary on/off switching function. The material provides superior electrical properties, while allowing the size of the transistor to be shrunk beyond limits being reached today.
In February,IBM revealed a first-of-its-kind, on-chip memory technology that features the fastest access times ever recorded in eDRAM (embedded dynamic random access memory).
Then in March, IBM unveiled a prototype optical transceiver chipset capable of reaching speeds at least eight-times faster than optical components available today.
