The 64th annual IEDM conference, sponsored by the IEEE Electron Devices Society, will be held December 1-5, 2018 in San Francisco. Let’s have a preview of the latest breakthroughs in transistors and related micro/nanoelectronics devices.
Since the integrated circuit (IC) was invented in the late 1950s, the continued scaling of transistors and related devices to smaller dimensions and higher levels of integration has led to increasingly powerful computers and other electronic systems. Continued scaling has now become tremendously expensive, yet it remains vital to developing the ultra-fast, lower-power processors and denser memories needed for demanding applications such as artificial intelligence (AI), graphics processing, cloud computing and others. Two noteworthy late-news papers, from Samsung and Imec, will describe paths to extreme scaling in advanced CMOS logic devices and DRAM memories, respectively.
- First Steps Toward 3nm CMOS Technology: Samsung researchers will describe their 3nm CMOS technology featuring gate-all-around (GAA) transistors with channels made from horizontal layers of nanosheets that are completely surrounded by gate structures. Samsung calls this a Multi-Bridge-Channel architecture, and says it is highly manufacturable as it makes use of ~90% of the company’s existing FinFET fabrication technology, requiring only a few revised photomasks. They built a fully functioning high-density SRAM macro with it. They say the process demonstrates excellent gate controllability (65 mV/dec subthreshold swing), 31% higher on-current than the company’s FinFET technology, and offers design flexibility because the nanosheet channel widths can be varied by means of direct patterning. (Paper #28.7, "3nm GAA Technology Featuring Multi-Bridge-Channel FET for Low-Power and High-Performance Applications," G. Bae et al, Samsung)
- Scaling DRAM Technology To 16nm And Beyond: DRAM memory technology is used in virtually all electronic systems because of its speed and density. DRAM memory comprises arrays of capacitor-transistor pairs which store data as electrical charge in the capacitor; the presence of charge indicates "1" and its absence "0." Manipulation of these digits is the basis of computer programming. It’s difficult to scale DRAM to the 16nm generation and beyond because of space limitations which make it hard to pack enough capacitance within the pitch. Imec researchers used an atomic layer deposition (ALD) process to pattern and build a novel 11nm pillar-shaped capacitor using new dielectric materials (SrTiO3, or STO). By tailoring the material properties of the capacitor and the SrRuO3 (SRO) epitaxial template on which it was grown, the researchers achieved a very high dielectric constant (k~118) and low electrical leakage (10-7 A/cm2 at ±1V). This means that pillar-shaped capacitors can be used instead of existing cup-shaped capacitors, without paying too great a penalty in terms of reduced data-storage capability. These results make the STO capacitors suitable for continued scaling for 16nm and smaller DRAMs. (Paper #2.7, "High-Performance (EOT<0.4nm, Jg~10-7 A/cm2) ALD-Deposited Ru/SrTiO3 Stack for Next-Generation DRAM Pillar Capacitor," M. Popovici et al, Imec)
The 2018 IEDM will also feature special Focus Sessions on the following topics:
- Quantum Computing Devices– Quantum computing will enable new types of algorithms to tackle problems in areas from materials science to medicine to artificial intelligence. Starting from an applications perspective, IEDM attendees will hear about different approaches to address fundamental questions at the device level; progress achieved so far; and next steps.
- Future Technologies Towards Wireless Communications: 5G and Beyond – 5G technology will drastically improve accessibility, bandwidth, performance and latency, but as it triggers fundamentally new applications it also will impose unique hardware requirements. This session will set a big picture view, then narrow down to how innovations in CMOS technologies, devices, filters, transceivers and antennas will enable the 5G platform.
- Interconnects to Enable Continued Technology Scaling – This session will provide a holistic perspective of interconnect scaling challenges and solutions. It will address the drivers of future interconnect architectures, the process options likely to be implemented in manufacturing, and how they will be tuned to ensure circuit reliability is maintained.
Intel Integrates e-MRAM With 22nm FinFETs: Embedded non-volatile memory (e-NVM) technologies, which retain data when power is turned off, are essential for Internet of Things (IoT), mobile and other applications, but the dominant embedded technology, e-flash, suffers from cost and scaling issues. Embedded MRAM (magnetoresistive random access memory), with its low manufacturing costs and high data retention and switching endurance, is a compelling alternative. It also has the potential to replace other types of embedded memory besides e-flash, and to serve as a building block for future logic devices as well. Integrating MRAM with mainstream CMOS technology has been problematic for various reasons, but Intel researchers will describe the successful integration of embedded MRAM into the company’s ultra-low-power 22nm FinFET CMOS technology on full 300mm wafers. The work represents a major step forward toward commercial use of the technology for high-performance, low-power applications. The magnetic tunnel junction-based memory cells are built from dual MgO magnetic tunnel junctions (MTJs) separated by a CoFeB-based layer in a 1 transistor-1 resistor (1T-1R) configuration in the interconnect stack. To demonstrate their performance, Intel built 7.2 Mb MRAM arrays which achieved industry-leading data retention (10 years with <1e-6 error rate at 200ºC) and endurance (>106 write endurance).
Highly Integrated Self-Aligned 3D Crosspoint Storage-Class Memory (SCM): Storage-class memories are an evolving class of high-density solid-state devices that attempt to combine the speed and small footprints of "working" computer memory such as DRAM with the non-volatility of flash memory at a low cost per bit. Researchers from SK Hynix will discuss a novel 3D crosspoint memory cell for use in SCMs that is built from new phase-change materials integrated with a chalcogenide selector device. The researchers fabricated the cells using self-aligned processes and precise materials-engineering techniques to preserve the electrical characteristics of these sensitive materials, which were integrated into a high-density 2z nm two-deck architecture for the first time. The devices demonstrated a read latency of <100 ns in a 16 Mb test array, which the researchers say is suitable for use in a 128 Gb SCM. (Paper #37.1, "High-Performance, Cost-Effective 2z nm Two-Deck Crosspoint Memory Integrated by Self-Align Scheme for 128 Gb SCM," T. Kim et al, SK Hynix)
Highest-Density 3DS Stacked FinFETs: Imec researchers will report on 3D stacked FinFETs that have the tightest pitches ever reported in such a stacked architecture – 45nm fin pitch and 110nm gate pitch. The 3D architecture makes use of a sequential integration process yielding tight alignment between very thin top and bottom Si layers. The junction-less devices in the top layer were fabricated and transferred using low-temperature (≤525ºC) processes to avoid performance degradation, and a 170nm dielectric was used to bond the two wafers. The top layer is so thin that the bottom layer could be patterned right through it by means of 193nm immersion lithography, which connects the two via local interconnect. The researchers evaluated various gate stacks, ultimately choosing TiN/TiAl/TiN/HfO2 with a LaSiOx dipole inserted into the stack. The combination demonstrated good threshold voltage tuning, reliability and low-temperature performance. (Paper #7.1, "First Demonstration of 3D Stacked FinFETs at a 45nm Fin Pitch and 110nm Gate Pitch Technology on 300mm Wafers," A. Vandooren et al, Imec)
Ge Channels For CMOS: To build higher-performance CMOS devices, replacing their silicon (Si) channels with ones made from germanium (Ge) is a promising approach because Ge has greater electron and hole mobility than Si. Ge P-FETs have shown great potential and SiGe P-FETs are commonly used in CMOS technologies. However, one issue is that CMOS devices are built from both N-FETs and P-FETs and it has been challenging to build high-quality Ge N-FET gate stacks because of internal material defects and high contact resistance. TSMC researchers will report how they overcame these N-FET roadblocks to achieve low Dit hysteresis-free P- and N-type Ge nanowire gate stacks combined with record low N-FET/metal contact resistivity (1.6e-9Ωcm2). Key to the effort was a multi-layer in-situ doped epitaxy process that enabled high dopant activation. Based on this they built the industry’s first vertically stacked Ge high-k nanowire gate stacks that meet all requirements for use in CMOS devices, and demonstrated high performance GAA Ge nanowire P-FETs with diameter scaling down to 6nm. The work paves the way for the possibility of fully complementary Ge-based devices in future technology nodes. (Paper 21.1, "Ge CMOS Gate Stack and Contact Development for Vertically Stacked Lateral Nanowire FETs," M.J.H. van Dal et al, TSMC)
InGaAs Channels For High-Mobility N-FET Nanosheets: IBM researchers, on the other hand, did look to III-V materials as a replacement for Si channels. They monolithically integrated high-performance InGaAs gate-all-around nanosheet N-FETs on Si using what they call a "Template-Assisted-Selective-Epitaxy" (TASE) process designed to integrate high-mobility material formed into nanoscale sheets. The nanosheets are scaled to 10nm thicknesses and the transistors have <40nm gate lengths, with the gate metal wrapping around the channel for optimal gate control. The devices demonstrated excellent current drive capability (Ion=355μA/μm), as well as subthreshold swing of 72 mV/decade. The researchers say device performance can be further improved by scaling gate length/nanosheet dimensions. The devices are compatible with current silicon manufacturing tooling. (Paper #39.2, "High-Performance InGaAs Gate-All-Around Nanosheet FET on Si Using Template-Assisted Selective Epitaxy," S. Lee et al, IBM)
CMOS-Compatible Graphene Interconnects: Integrating graphene into the interconnect scheme holds the promise of increasing performance and limiting power consumption in next-generation CMOS ICs, as graphene offers high conductivity and is not prone to electromigration. One of the main challenges for practical implementations are the high temperatures typically needed to form graphene (800-1000ºC), which would damage the active devices already fabricated at the front-end-of-the-line. University of California-Santa Barbara researchers will report on a new approach in which a low-temperature (300ºC) pressure-assisted solid-phase diffusion process enables the growth and doping of multi-level CMOS-compatible graphene nanoribbons. These nanoribbons demonstrated a markedly lower contact resistance (<20 Ω-µm) than copper interconnect, yielded a ~4x increase in device performance, and showed negligible electromigration under 100 MA/cm2 at >100ºC. These results point to a practical and industry-compatible approach toward exploiting the unique electrical properties of graphene in silicon-based CMOS ICs. (Paper #34.5, "CMOS-Compatible Doped-Multilayer-Graphene Interconnects for Next-Generation VLSI," J. Jiang et al, Univ. California-Santa Barbara.)
Full details, including links for registration, are on the IEDM website.