During the latest conference call following the company's announcement of its Q3 2019 results, TSMC had the chance to comment on the progress made to its 5nm and 7nm manufacturing processes, and the implementation of EUV in the chip making procedure.

C. C. Wei, Vice Chairman & CEO of TSMC, expects that demand from both smartphone- and high-performance computing-related applications in Q4 to continue to increase, thanks to the company's 7-nanometer technology that powers these applications.

He also expects the demand for 5G infrastructure and 5G smartphones to lead to the the increase of TSMC's CapEx for this year. The company expects a faster ramp of 5G smartphones as compared to 4G with the penetration rate of 5G smartphones to reach mid-teens percentage of the total smartphone market in 2020.

This means that the silicon content of 5G smartphones will be substantially higher than that of 4G smartphones. That is due to increasing functionalities and additional ICs for more camera, RF circuit, modem, power management IC, etc.

TSMC expects its 5 nm (N5) manufacturing technology to provide significant benefits when it comes to performance, power, and area scaling, which is why the contract maker of semiconductors expects a tangible number of its customers to adopt this process.

And, with a forecast for aggressive demand paired with some early preparation in installing new equipment, TSMC believes that its N5 technology will ramp even quicker than its 7 nm (N7) process.

Mr. Wei said that the 5 nm N5 technology has already entered risk production with good yield. He added that N5 will adopt the EUV "extensively" and is well on track for volume production in the first half of next year.

With 80%, 8-0, logic density gain and about a 20% speed gain compared with the 7-nanometer, TCMC's N5 technology is true full node stride from the company's N7. "We believe it will be the foundry industry's most advanced solution with the best density, performance and power until our 3-nanometer arrives," Mr. Wei said.

With N5, the initial ramp will be driven by both mobile and HPC applications. TSMC's executive is confident that 5-nanometer will have a strong ramp and be a large and long-lasting node for TSMC.

TSMC is also working with customers on 3nm N3 and Mr. Wei said that the technology development progress "is going well." TSMC's N3 will be another full node from the foundry's N5 with PPA gain similar to the gain from N7 to N5. "We expect our 3-nanometer technology will be the most advanced foundry technology in both PPA and transistor technology when it is introduced," Mr. Wei said.

TSMC CEO also talked about the ramp-up of N7, N7+ and the status of N6. Today, TSMC is completing its second year ramp of N7. The company continues to see very strong demand across a wide spectrum of products for mobile, HPC and IoT applications. TSMC's N7 process is the industry's first commercially available EUV lithography technology. N7+ provides 15% to 20% higher density with improved power consumption when compared to N7. That is already in high volume production with yield similar to N7. TSMC expects the strong demand for N7+ continue into next year and are increasing Capex to meet this demand for multiple customers.

TCMS's 6nm (N6) process provides a migration path for the second-wave N7 product as its design rules are 100% compatible with N7 while providing 18% logic density gain with performance-to-cost advantage. The N6 uses one more EUV layer than N7+. Mr. Wei said that N6 risk production is scheduled to beginin first quarter next year with volume production starting before the end of 2020. He reaffirmed 7-nanometer will contribute more than 25% of TSMC's wafer revenue in 2019 and expects even higher percentage in 2020 due to worldwide development of 5G, accelerated demand from HPC, mobile and other application continue to grow.

Mr. Wei also talked about TSMC's advanced packaging business. The company's advanced packaging solutions enable system integration with wafer level process, allowing integration of front-end wafer process and back-end chip packaging. The solutions consist of CoWoS, InFO, System on Integrated Chips or SoIC and the Wafer on Wafer or WoW. "We are seeing strong momentum for CoWoS and InFO for HPC applications as we continue to enlarge the integrated chip area to about -- to above 2 reticle size in 1 module. We are also working with a few leading customers on SoIC, which is an industry-leading 3D-IC packaging solution," Mr. Wei said.

SoIC enables 3D integration of multiple chips in close proximity to deliver the best possible performance, power and form factor. TSMC targets to start production in 2021 time frame with early adoption by HPC applications.

Over the past 3 years, there were some kind of challenges in EUV manufacturing process in terms of power, throughput, pellicle, etc.

Mr. Wei said that at TSMC, the EUV lithography technology is now in the production stage. But the company is stil not happy with that. "We are still improving availability. We have output power of 250 watts, as we expected. Now we can operate the tool with 250 watts consistently. However, there's still something that we need to improve so that we can improve the throughput, the availability so you can reduce the costs," he said.

TSMC's executive also said that TSMC's 28-nanometer technology node is currently in low utilization, not up to TSMC's expectations, as a result to overcapacity. He expects 2 years later from now to return in the high utilization.

For 16 nm and 12 nm nodes, today TSMC is still in a very healthy utilization. Referring to rival Samsung, Mr. Wei said that if TSMC's competitor continues to increase the capacity just like 28-nanometer's node, he expects the same overcapacity to occur in 12 nm.