Cadence, Mentor Graphics, Synopsis And Ansys Offering Tools For Intel's 14nm Tri-Gate Technology
Intel collaborated with Synopsys, ANSYS, Mentor Graphics and Cadence Design Systems to facilitate the adoption of its 14 nanometer (nm) Tri-Gate process technology by Intel Custom Foundry customers.
The partnerships will boost its 14nm design platform for cloud infrastructure and mobile market applications. These alliances are an extension of the work on the Intel Custom Foundry 22nm process design platform to the 14nm platform.
Intel's 14nm process technology uses the second generation of 3-D Tri-Gate transistors. These Tri-Gate transistors enable chips to operate at lower voltage with lower leakage, providing a combination of improved performance and energy efficiency compared to planar transistors.
Mentor Graphics's circuit simulation and sign-off tools are fully enabled for Intel's 14nm Tri-Gate process technology for customers of Intel Custom Foundry. Mentor and Intel Custom Foundry are providing models and rule decks for circuit simulation, design rule checking (DRC) and layout vs. schematic checking (LVS) for mobile and cloud infrastructure applications. Collaboration efforts so far have resulted in a 2X speed up in full chip Calibre DRC verification run times, the companies say. Readiness of the Mentor's baseline circuit simulation and sign-off tools on Intel Custom Foundry 14nm design platform provides Intel's customers with access to Intel's 14nm technology and Mentor's simulation and verification tools.
Intel has also worked with Synopsys to enable broad SoC designs for Intel's 14-nm Tri-Gate process technology . The Intel Custom Foundry 14-nm design platform supports Synopsys' Galaxy Design Platform tools and RTL-to-GDSII methodology, high-performance DesignWare Memory Compiler intellectual property (IP), and advanced interface IP. The design tools and IP are now ready for Intel's 14-nm foundry process technology.
Support for Synopsys Galaxy Design Platform is available today for Intel Custom Foundry 22-nm and 14-nm process technologies. DesignWare Memory Compilers and DDR3/2 PHYs are also available today.
Cadence Design Systems and Intel have also together enabled the custom/analog flow, including Spectre APS, Virtuoso Schematic Editor, Virtuoso Layout Suite and Virtuoso Analog Design Environment for the 14nm Tri-Gate process. The companies are also collaborating on the development of the Cadence digital flow featuring Encounter Digital Implementation System, QRC Extraction Solution, and Tempus Timing Signoff Solution. Using these design flows, Intel's customers can leverage performance and area benefits of Intel's 14nm process technology.
Cadence is also delivering the LPDDR4-3200 PHY for Intel Custom Foundry's 14nm Low Power design platform. With data rates of up to 3200Mbps and a 1.6 GHz memory clock, this latest and most advanced memory PHY IP realizes the full capabilities of LPDDR4 technology. Cadence LPDDR4-3200 PHY IP is backward compatible with LPDDR3 memories and supports package on package (POP) and memory on PCB systems.
In addition, ANSYS and Intel Custom Foundry teams have developed reference flows around ANSYS RedHawk for system on chip power and electromigration (EM) sign-off, ANSYS Totem for custom intellectual property power and EM integrity and ANSYS PathFinder for full-chip ESD validation.
Intel's 14nm process technology uses the second generation of 3-D Tri-Gate transistors. These Tri-Gate transistors enable chips to operate at lower voltage with lower leakage, providing a combination of improved performance and energy efficiency compared to planar transistors.
Mentor Graphics's circuit simulation and sign-off tools are fully enabled for Intel's 14nm Tri-Gate process technology for customers of Intel Custom Foundry. Mentor and Intel Custom Foundry are providing models and rule decks for circuit simulation, design rule checking (DRC) and layout vs. schematic checking (LVS) for mobile and cloud infrastructure applications. Collaboration efforts so far have resulted in a 2X speed up in full chip Calibre DRC verification run times, the companies say. Readiness of the Mentor's baseline circuit simulation and sign-off tools on Intel Custom Foundry 14nm design platform provides Intel's customers with access to Intel's 14nm technology and Mentor's simulation and verification tools.
Intel has also worked with Synopsys to enable broad SoC designs for Intel's 14-nm Tri-Gate process technology . The Intel Custom Foundry 14-nm design platform supports Synopsys' Galaxy Design Platform tools and RTL-to-GDSII methodology, high-performance DesignWare Memory Compiler intellectual property (IP), and advanced interface IP. The design tools and IP are now ready for Intel's 14-nm foundry process technology.
Support for Synopsys Galaxy Design Platform is available today for Intel Custom Foundry 22-nm and 14-nm process technologies. DesignWare Memory Compilers and DDR3/2 PHYs are also available today.
Cadence Design Systems and Intel have also together enabled the custom/analog flow, including Spectre APS, Virtuoso Schematic Editor, Virtuoso Layout Suite and Virtuoso Analog Design Environment for the 14nm Tri-Gate process. The companies are also collaborating on the development of the Cadence digital flow featuring Encounter Digital Implementation System, QRC Extraction Solution, and Tempus Timing Signoff Solution. Using these design flows, Intel's customers can leverage performance and area benefits of Intel's 14nm process technology.
Cadence is also delivering the LPDDR4-3200 PHY for Intel Custom Foundry's 14nm Low Power design platform. With data rates of up to 3200Mbps and a 1.6 GHz memory clock, this latest and most advanced memory PHY IP realizes the full capabilities of LPDDR4 technology. Cadence LPDDR4-3200 PHY IP is backward compatible with LPDDR3 memories and supports package on package (POP) and memory on PCB systems.
In addition, ANSYS and Intel Custom Foundry teams have developed reference flows around ANSYS RedHawk for system on chip power and electromigration (EM) sign-off, ANSYS Totem for custom intellectual property power and EM integrity and ANSYS PathFinder for full-chip ESD validation.
