IBM's Power6 Processors to Hit 5.6GHz
At the International Solid-State Circuits Conference (ISSCC) in San Francisco, IBM said its upcoming Power6 microprocessor for servers will run at unprecedented speeds while keeping a lid on power requirements and heat.
The Power6 is a multicore processor designed for higher-end servers running the Unix operating system. Built around silicon-on-insulator (SOI) and other technologies, the Power6 is the follow-on processor to the company?s current Power5 architecture. IBM indicated that the 65-nm Power6 processor will operate in excess of 4-GHz. Intel's Itanium 2 server processor today tops out at 1.66GHz, while the Pentium 4 for desktops currently reaches speeds of 3.8 GHz.
The company also described a 5.6-GHz Power6 processor with 64-Kb of Level 1 data cache. The processor is said to have an eight-way, set-associative design with a two-stage pipeline supporting two independent reads or one writes per cycle.
"In Power6, we basically combined everything we could (throw) at it in terms of fundamental atoms and molecules all the way out to what we knew would be the software that would run on top of that system," said Bernard Meyerson, chief technologist of IBM's Systems and Technology Group.
"Despite the speeds, it will have a lower power density than in some chips found in today's desktops," Meyerson added.
IBM also makes use of a 5-GHz duty-cycle correction clock distribution network for the processor. In the network, the company implements a copper distribution wire that is 3 microns wide and 1.2 microns thick.
In another paper, IBM described low-latency fixed-point and binary floating-point units for the Power6. The floating-point unit incorporates ?many microarchitectures, logic, circuit, latch and integration techniques to achieve 6-cyle, 13-FO4 pipeline,? according to the company?s paper.
The Power6 design uses dual power supplies, a logic supply in the 0.9-to-1.2 Volt range and an SRAM power supply at about 150-mV higher.
The International Solid-State Circuits Conference (ISSCC) runs through Friday.
The company also described a 5.6-GHz Power6 processor with 64-Kb of Level 1 data cache. The processor is said to have an eight-way, set-associative design with a two-stage pipeline supporting two independent reads or one writes per cycle.
"In Power6, we basically combined everything we could (throw) at it in terms of fundamental atoms and molecules all the way out to what we knew would be the software that would run on top of that system," said Bernard Meyerson, chief technologist of IBM's Systems and Technology Group.
"Despite the speeds, it will have a lower power density than in some chips found in today's desktops," Meyerson added.
IBM also makes use of a 5-GHz duty-cycle correction clock distribution network for the processor. In the network, the company implements a copper distribution wire that is 3 microns wide and 1.2 microns thick.
In another paper, IBM described low-latency fixed-point and binary floating-point units for the Power6. The floating-point unit incorporates ?many microarchitectures, logic, circuit, latch and integration techniques to achieve 6-cyle, 13-FO4 pipeline,? according to the company?s paper.
The Power6 design uses dual power supplies, a logic supply in the 0.9-to-1.2 Volt range and an SRAM power supply at about 150-mV higher.
The International Solid-State Circuits Conference (ISSCC) runs through Friday.
