Intel Details 32 nm Process, 'Jasper Forest' Embedded CPU
Prior to the Intel Developers Forum (IDF), Intel today disclosed information about next-generation Intel Xeon processors - codenamed "Jasper Forest" as well as the upcoming 32nm logic technology with the development the 'Westmere' microprocessors.
Intel's Developer Forum will be held this month (22nd-24th) in San Fransisco.
Highlights of this year's announcements include information about the 32nm SoC, the introduction of the 'Jasper Forest' CPUs, chip design and manudacturing details on the Larabee, Westmere SOC, SSDs, news on Clarksfield platform where Nehalem comes to laptops and finally information on newly designed MIDs, Moblin v2 and the upcoming Moorestown platform.
Intel has provided some details on its future family of low-power integrated Intel Xeon embedded processors ("Jasper Forest") and its 32nm CPU process today.
Intel's Upcoming 32nm Logic Technology
Intel disclosed new details today about the company's forthcoming 32nm process technology for the new 2010 Core family of processors and future SoC products. For the first time Intel has developed a full-featured SoC process technology to complement the CPU-specific technology, both versions use second-generation high-k + metal gate transistors for leading performance and power characteristics.
The company outlined new details for both versions of the 32nm process, as well as a new 45nm high-k + metal gate milestone, which will be discussed in various sessions at next week?s Intel Developer Forum and in papers at the International Electron Devices Meeting in December.
Intel said that it has shipped >200 million 45nm CPUs using HK+MG transistors since Nov 2007. Intel's 32nm process is certified and Westmere CPU wafers are moving through the factory in support of planned Q4 revenue production.
The company claims that the 32nm second-generation high-k metal gate transistors have the highest-reported performance (as measured by drive current) of any 32nm or 28nm technology
The NMOS transistors have 19 percent performance improvement over their 45nm counterparts, while the PMOS transistors have a 28 percent performance improvement too.
Intel also claims that its 32nm second generation high-k metal gate transistors have the highest-reported density for any 32nm or 28nm technology
Transistor gate pitch, a measurement for density, is 112.5nm. Gate pitch indicates how tightly transistors can be packed in a given area. Higher density means more transistors in a given area of silicon for increased functionality and better performance.
For the first time, Intel has developed a full-featured SoC process technology to complement the CPU-specific technology. Some special features of this process are ultra low power transistors with second-generation high-k + metal gate for low standby/always-on circuit applications; and high voltage I/O transistors, Intel said. This process also includes new high-precision and high-quality passive components specifically needed for SoCs, such as resistors, capacitors and inductors, the company added.
Introducing the "Jasper Forest" CPUs
Intel also disclosed new information about next-generation Intel Xeon processors - codenamed "Jasper Forest" ? for communications and storage applications, due in early 2010. With Jasper Forest, Intel engineers have, for the first time, integrated PCI Express (PCIe) in a dual-processing Xeon processor, which facilitates dense storage and communications solutions such as IPTV, VoIP, NAS, SAN and wireless radio network controllers.
Intel claims that Jasper Forest maintains the performance of Intel architecture (Nehalem), while lowering system power consumption by 27 watts when compared to the Intel Xeon 5500 series processors. The dual-processing solution integrates two Jasper Forest processors with 16 PCIe Generation 2.0 lanes each and is paired with the Intel 3420 chipset platform controller hub. This integration of the I/O hub via PCIe enables significant power and space savings, resulting in one of the highest performance-per-watt Intel Xeon chips ever.
Jasper Forest also provides a scalable option to design with a single-core, 23-watt processor to a quad-core, 85-watt processor using the same socket. The interoperability of Intel architecture can alleviate the frustration of costs and headaches associated with using different architectures. Additional technical features of Jasper Forest include:
- Non-transparent bridging functionality allows multiple systems to seamlessly connect over a PCIe link, removing the need for an external PCIe switch.
- Integrated Redundant Array of Independent Disks (RAID) acceleration, which is advantageous for storage customers migrating to Intel architecture or transitioning RAID for core optimization.
- Integrated Asynchronous Dynamic Random Access Memory Self-Refresh memory provides a backup solution to help protect critical data in the event of a power failure.
The processors, expected to be available by early 2010, will be offered with 7-year lifecycle support and are addressed to market segments such as communications, storage, wireless infrastructure, routers, military and security.
Highlights of this year's announcements include information about the 32nm SoC, the introduction of the 'Jasper Forest' CPUs, chip design and manudacturing details on the Larabee, Westmere SOC, SSDs, news on Clarksfield platform where Nehalem comes to laptops and finally information on newly designed MIDs, Moblin v2 and the upcoming Moorestown platform.
Intel has provided some details on its future family of low-power integrated Intel Xeon embedded processors ("Jasper Forest") and its 32nm CPU process today.
Intel's Upcoming 32nm Logic Technology
Intel disclosed new details today about the company's forthcoming 32nm process technology for the new 2010 Core family of processors and future SoC products. For the first time Intel has developed a full-featured SoC process technology to complement the CPU-specific technology, both versions use second-generation high-k + metal gate transistors for leading performance and power characteristics.
The company outlined new details for both versions of the 32nm process, as well as a new 45nm high-k + metal gate milestone, which will be discussed in various sessions at next week?s Intel Developer Forum and in papers at the International Electron Devices Meeting in December.
Intel said that it has shipped >200 million 45nm CPUs using HK+MG transistors since Nov 2007. Intel's 32nm process is certified and Westmere CPU wafers are moving through the factory in support of planned Q4 revenue production.
The company claims that the 32nm second-generation high-k metal gate transistors have the highest-reported performance (as measured by drive current) of any 32nm or 28nm technology
The NMOS transistors have 19 percent performance improvement over their 45nm counterparts, while the PMOS transistors have a 28 percent performance improvement too.
Intel also claims that its 32nm second generation high-k metal gate transistors have the highest-reported density for any 32nm or 28nm technology
Transistor gate pitch, a measurement for density, is 112.5nm. Gate pitch indicates how tightly transistors can be packed in a given area. Higher density means more transistors in a given area of silicon for increased functionality and better performance.
For the first time, Intel has developed a full-featured SoC process technology to complement the CPU-specific technology. Some special features of this process are ultra low power transistors with second-generation high-k + metal gate for low standby/always-on circuit applications; and high voltage I/O transistors, Intel said. This process also includes new high-precision and high-quality passive components specifically needed for SoCs, such as resistors, capacitors and inductors, the company added.
Introducing the "Jasper Forest" CPUs
Intel also disclosed new information about next-generation Intel Xeon processors - codenamed "Jasper Forest" ? for communications and storage applications, due in early 2010. With Jasper Forest, Intel engineers have, for the first time, integrated PCI Express (PCIe) in a dual-processing Xeon processor, which facilitates dense storage and communications solutions such as IPTV, VoIP, NAS, SAN and wireless radio network controllers.
Intel claims that Jasper Forest maintains the performance of Intel architecture (Nehalem), while lowering system power consumption by 27 watts when compared to the Intel Xeon 5500 series processors. The dual-processing solution integrates two Jasper Forest processors with 16 PCIe Generation 2.0 lanes each and is paired with the Intel 3420 chipset platform controller hub. This integration of the I/O hub via PCIe enables significant power and space savings, resulting in one of the highest performance-per-watt Intel Xeon chips ever.
Jasper Forest also provides a scalable option to design with a single-core, 23-watt processor to a quad-core, 85-watt processor using the same socket. The interoperability of Intel architecture can alleviate the frustration of costs and headaches associated with using different architectures. Additional technical features of Jasper Forest include:
- Non-transparent bridging functionality allows multiple systems to seamlessly connect over a PCIe link, removing the need for an external PCIe switch.
- Integrated Redundant Array of Independent Disks (RAID) acceleration, which is advantageous for storage customers migrating to Intel architecture or transitioning RAID for core optimization.
- Integrated Asynchronous Dynamic Random Access Memory Self-Refresh memory provides a backup solution to help protect critical data in the event of a power failure.
The processors, expected to be available by early 2010, will be offered with 7-year lifecycle support and are addressed to market segments such as communications, storage, wireless infrastructure, routers, military and security.
