This year’s International Solid-State Circuits Conference (ISSCC) inludes paper presentations related to 5G/LTE, machine learning, NAND and DRAM memories, rather than advancements in Silicon IC technology predicted by Moore’s Law.

Pursuing Moore’s Law becomes increasingly more challenging from technology and economic perspectives.

Stimulated by these difficulties, the solid-state circuit community is exploring a multiplicity of paths for further development: from novel technologies (innovative devices and integration techniques, such as qubits, spintronics, 3D, and photonic integration), to original approaches (such as Artificial Intelligence (AI) and Machine Learning (ML)), to new applications (such as wearable electronics, IoT, virtual reality, autonomous driving, robotics, and many more).

Interestingly, this year’s event has no papers on 5-nm SRAMs or test chips, although it does include talks on a handful of fast 7-nm networking chips. There also also no papers describing flagship CPUs.

Let's have a look at some interesting presentaions of ISSCC 2019, which
will be held February 17-21 in San Francisco.

IBM engineers will describe the Summit and Sierra supercomputers, currently the most powerful systems in the world. The processor session also hosts a paper on a robot controller that scales from 37 to 238 mW at 80–365 MHz using an Intel 22-nm process intended as a rival to fully depleted silicon-on-insulator.

Yann LeCun, director of AI research at Facebook and the father of convolutional neural networks, will describe the road to unsupervised learning, where machines learn like people do from their environment.

Samsung wil ltalk about its mobile accelerator for deep learning, which delivers up to 11.5 tera-operations/second (TOPS) at 0.5 V and fits into 5.5 mm2 in an 8-nm process. It packs 1,024 multiply-accumulate units in a dual-core design and delivers a tenfold performance boost over the previous state of the art.

Toshiba will describe a 16-nm SoC for robocars that delivers 20.5 TOPS in a 94.52-mm2 die that includes 10 processors, four DSPs, and eight accelerators. It performs ASIL-B–compliant image recognition and ASIL-D–compliant control processes.

In-memory computing ha sbeen a hot topic lately, mainly as an pproach in AI acceleration. National Tsing Hua University will detail a chip that delivers 53.17 TOPS/W in binary mode using resistive RAM. The device sports an operation latency of 14.6 ns.

Samsung will also detail a 14-nm, 38.4-mm2 chip that supports 2G, 3G, LTE, and both standalone and non-standalone 5G modes. It uses 14 receive and two transmit paths to deliver up to 3.15 Gbits/s down and 1.27 Gbits/s up.

The South Korean company will present a power supply modulator for sub-6-GHz 5G networks, supporting 100-MHz bandwidth for envelope tracking and offering an 88% efficiency. It will also detail a power management IC for a 5G millimeter-wave transceiver capable of 90 ns/V and 110 ns/V for up- and down-tracking.

The chips are part of Samsung’s Exynos Modem 5100, a 5G chipset supporting both sub-6-GHz and mmWave networks.

Intel will present a 28-nm 4G/5G transceiver for sub-6-GHz bands in zero-IF and 10.56-GHz IF for mmWave bands. It sports an M-PHY Gear 3 interface for MIMO and up to 800-MHz bandwidth with carrier aggregation. It is part of the latest 5G chipset that Intel announced earlier this month.

Huawei, eSilicon, Mediatek, and IBM will show 7-nm devices delivering data rates up to 128 Gbits/s, generally using PAM-4 modulation.

In the storage segment, Toshiba will present a 1.33-Tb, 4-bit/cell (QLC) 3D-NAND chip using a 96-layer design 3D-NAND. It packs 8.5 Gbits/mm2.

Western Digital will detail a 512-Gbit, 3-bit/cell chip using a record 128-layer stack. It places control circuits under the memory array and delivers a write throughput of 132 MBytes/s.

For its part, Samsung will show a 512-Gbit 3-bit/cell chip delivering 1.2 Gbits/s. It reduces worldline and bitline setup times to boost read and write performance.

In embedded memories, Intel will demonstrate advances in ReRAM and MRAM for its 22-nm FinFET node. It is said that the 10.1-Mb/mm2 ReRAM macro is a viable candidate for next-generation MCUs given its relatively low cost and high speed. A 7-Mbit STT-MRAM uses a write-verify-write scheme and offset cancellation sensing.

In DRAM, Samsung will present a 10-nm–class LPDDR5 chip. It reduces read and write power consumption by 21% and 33%, respectively, compared to LPDDR4X by using dynamic voltage frequency scaling and a deep-sleep mode.

S. Korean SK Hynix will describe a 16-Gbit DDR5 SDRAM that delivers 6.4 Gbits/s/pin. Energy efficiency is improved more than 30% over the prior DDR4.