JEDEC Solid State Technology Association today announced the publication of JESD209-3 LPDDR3 Low Power Memory Device Standard, which is inteneded to meet the perforamnce demands of mobile devices. LPDDR3 offers a higher data rate, improved bandwidth and power efficiency, and higher memory densities over its predecessor, LPDDR2. Developed by JEDEC?s JC-42.6 Subcommittee for Low Power Memories, the LPDDR3 Low Power Memory Device Standard is available for free download from the JEDEC.

LPDDR3 achieves a data rate of 1600Mbps (versus 1066Mbps for LPDDR2) through the addition of new features, including:

- Write-Leveling and CA Training: These features allow the memory controller to compensate for signal skew, ensuring that data input setup and hold timing as well as command and address input timing requirements are met while operating at the industry's fastest input bus speeds

- On Die Termination (ODT): This optional feature enables a light termination to LPDDR3 data lanes to improve high-speed signaling with minimal impact on power consumption, system operation and pin count

- Low I/O capacitance

As with LPDDR2, LPDDR3 supports both Package on package and discrete packaging types in order to meet the requirements of a wide array of mobile devices. LPDDR3 will preserve the power-efficient features and signaling interface of LPDDR2, allowing for fast clock stop/start, low-power self-refresh, and smart array management.