Despite industry efforts, Extreme ultraviolet (EUV) lithography is producing random errors called stochastic effects and researchers are trying to understand their root causes.

EUV systems are finally in place to produce high-end chips. They have finally been improved in order to offer the throughput required by commercial fabs, and they are already being used by both TSMC and Samsung for some aspects of their next-generation 7nm processes.

However, shortcomings are still in place, and are expected to be more serious as chip makers will try to move to even more advanced manufacturing nodes.

EUV consists of several components that must come together before chipmakers can insert use it. These include the scanner, power source, resists and masks.

While previously the EUV community talked about the problems faced in order to make the power source strong and reliable enough to maintain high wafer output, the recenty talks are related to photoresists and related issues as the top challenge for EUV.

The resists, which are light-sensitive polymers used to create patterns, are among the culprits that cause stochastics. By definition, stochastics describe events that have random variables. They are unpredictable and without a stable pattern.

In the case of EUV, photons hit a resist and cause a reaction. But with EUV, there might be a new and different reaction during each event or multiple events. And so EUV is prone to events involving stochastics. Generally, the industry blames the resists for the stochastics, but variations also can occur with the photomasks and other parts of EUV.

A leading-edge logic chip incorporates a billion or more tiny contacts. If there is a mishap in the EUV process, the chip could suffer from stochastic-induced failures or defects. In other words, a chip can fail with a defect in just one contact.

Starting from the 5nm, chipmakers may not be able to avoid these and other issues unless the industry comes up with some new breakthroughs.

Stochastics identified last year create unintended connections and holes. Among other issues, edge placement errors are forcing researchers to track a dozen new parameters across multiple areas to understand their root causes.

It is believed that engineers could eventually further shrink the currently printed 40nm metal gate pitches by applying improvements in materials, design and manufacturing processes. However, gate pitches have largely hit a wall, according to Imec researcher Ryoung-han Kim.

Masks may need to move to a high-k absorber. However, they may not be ready until second-generation EUV systems emerge in about 2024 targeting the 3nm node. Meanwhile, multibeam mask writers may help improve throughput, Kim said.

At least for the upper M0-M3 metal layers, Imec believes engineers will need to move to double patterning EUV as soon as next year to compensate for some of the issues. Although applying double patterning would increase the costs, it may spread to use at most metal layers until the next-generation systems are ready.

During the recent ISSCC 2019, Imec researchers described another way to address the stochastic errors. Imec’s sequential infiltration synthesis (SIS) adds inorganic elements to a photoresist to make features harder and more robust, enhancing patterning performance. Using the technique, Imec said it a 60% improvement in the sharpness known as intrafield local critical dimension uniformity (LCDU). It also saw a 10% decrease in line edge roughness.

Industry is forced to create tools that can identify where on a wafer the statistically random errors are likely to occur. However, researchers could ultimately develop functional IP blocks that could automate detection of at least some forms of EUV defects.

Dutch ASML, the developer and manufacturer of the EUV machines currently used in advanced fabs, gave an update on progress of 0.55 High-NA, the next generation for EUV. The systems are very large in size but allow printing finer features thanks to a higher numerical aperture.

ASML said that the first systems should be delivered to customers in late 2023 using doses of 40-60 millijoules/cm2 and running at up to 185 wafers/month. The dose level, about twice that of today’s 0.33NA systems, should help reduce stochastic errors and improve line-edge roughness, according to ASML. The new system will also able to print full, half and fractional images in already printed wafers, but that would slow the throughput levels.

In the area of resists, companies are trying to create proprietary resist formulas and test it at Imec’s fab.

Imec and KMLabs have announced a joint development to create a real-time functional imaging and interference lithography laboratory. This lab will enable imaging in resist on 300mm wafers down to 8nm pitch. Additionally, it will enable time-resolved nanoscale characterization of complex materials and processes, such as photoresist radiation chemistry, two-dimensional materials, nanostructured systems and devices, emergent quantum materials.

The ability to pattern ever-smaller feature sizes and denser pitches is significantly challenged due to a lack of fundamental understanding of EUV sub-picosecond exposure processes. Imec says that its attolab will enable the study of EUV photon absorption and subsequent ionization processes at unprecedented timescales from attoseconds to picoseconds. It is anticipated that the gain in fundamental understanding of material characteristics pave the way for the development of new lithographic materials and underlayers.

Imec’s attolab will also enable interference imaging to emulate high numerical aperture (NA) imaging at 13.5nm. This capability is planned to jump start development of the high-NA patterning ecosystem at imec in preparation for the planned ASML-imec High-NA lab, which will be centered around one of the first ASML EXE5500 High-NA (0.55NA) proto tools. By combining this High-NA interference capability with the current HVM-relevant EUV scanner (NXE:3400B) in imec’s cleanroom, imec and its partners will be able to explore the fundamental dynamics of photoresist imaging before the 0.55NA tools become available.

The future of EUV for the creation of more advanced chips -- including memories -- based on new logic processes is depending on the progress made by researchers.