ARM today introduced two new physical IP implementation solutions for its silicon partners to help simplify the path to implementation for their FinFET physical designs. ARM claims that the new Artisan Power Grid Architect will reduce overall design time by creating optimal SoC power grid layouts while ARM Artisan Signoff Architect will increases precision in managing on-chip variation over existing methodologies.

Artisan Power Grid Architect creates power-optimized networks and removes the need for implementation teams to apply detailed FinFET design rules, allowing extra time to explore power network options for a particular design. Additionally, Artisan Power Grid Architect automates critical aspects of floorplanning to improve overall power, performance and area (PPA), especially for power grid design. Artisan Signoff Architect adds enhancements and more precision to stage-based on-chip variation (SB-OCV) signoff methodologies, adding accuracy that is not supported in the existing IP model format.

Artisan Power Grid Architect and Artisan Signoff Architect are used exclusively with ARM Artisan advanced physical IP for TSMC 16nm FinFET (CLN16FF+). The beta release of Artisan Power Grid Architect for TSMC CLN16FF+ will be available October 2014, while Artisan Signoff Architect will be available for TSMC CLN16FF+ beta release in Q4 2014.