New Ultra-low-power Memory Dramatically Extends Battery Life For Mobile Devices
University of Illinois engineers have developed a form of ultra-low-power digital memory that is faster and uses 100 times less energy than similar available memory. The technology could give future portable devices much longer battery life between charges.
The flash memory used in mobile devices today stores bits as charge, which requires high programming voltages and is relatively slow. Industry has been exploring faster, but higher power phase-change materials (PCM) as an alternative. In PCM memory a bit is stored in the resistance of the material, which is switchable.
A group of University of Illinois engineers led by electrical and computer engineering professor Eric Pop managed to lower the power per bit to 100 times less than existing PCM memory by focusing on size: Rather than the metal wires standard in industry, the group used carbon nanotubes, tiny tubes only a few nanometers in diameter - 10,000 times smaller than a human hair. Since the energy consumption is essentially scaled with the volume of the memory bit, by using nanoscale contacts, engineers were able to achieve much smaller power consumption.
To create a bit, the researchers placed a small amount of PCM in a nanoscale gap formed in the middle of a carbon nanotube. They can switch the bit "on" and "off" by passing small currents through the nanotube.
Nanotubes also boast an extraordinary stability, as they are not susceptible to the degradation that can plague metal wires. In addition, the PCM that functions as the actual bit is immune to accidental erasure from a passing scanner or magnet.
Right now, a smart phone uses about a watt of energy and a laptop runs on more than 25 watts. Some of that energy goes to the display, but an increasing percentage is dedicated to memory.
Pop said that the new memory could power future cell phones or laptops whose batteries could last for weeks or months. Pop also believes that the nanotube PCM memory could increase an iPhone's energy efficiency so it could run for a longer time on a smaller battery, or even to the point where it could run simply by harvesting its own thermal, mechanical or solar energy - no battery required.
The low-power memory could also enable three-dimensional integration, a stacking of chips that has eluded researchers because of fabrication and heat problems, the researchers said.
A group of University of Illinois engineers led by electrical and computer engineering professor Eric Pop managed to lower the power per bit to 100 times less than existing PCM memory by focusing on size: Rather than the metal wires standard in industry, the group used carbon nanotubes, tiny tubes only a few nanometers in diameter - 10,000 times smaller than a human hair. Since the energy consumption is essentially scaled with the volume of the memory bit, by using nanoscale contacts, engineers were able to achieve much smaller power consumption.
To create a bit, the researchers placed a small amount of PCM in a nanoscale gap formed in the middle of a carbon nanotube. They can switch the bit "on" and "off" by passing small currents through the nanotube.
Nanotubes also boast an extraordinary stability, as they are not susceptible to the degradation that can plague metal wires. In addition, the PCM that functions as the actual bit is immune to accidental erasure from a passing scanner or magnet.
Right now, a smart phone uses about a watt of energy and a laptop runs on more than 25 watts. Some of that energy goes to the display, but an increasing percentage is dedicated to memory.
Pop said that the new memory could power future cell phones or laptops whose batteries could last for weeks or months. Pop also believes that the nanotube PCM memory could increase an iPhone's energy efficiency so it could run for a longer time on a smaller battery, or even to the point where it could run simply by harvesting its own thermal, mechanical or solar energy - no battery required.
The low-power memory could also enable three-dimensional integration, a stacking of chips that has eluded researchers because of fabrication and heat problems, the researchers said.
