Japanese researchers at Chuo University developed an SSD (solid state drive) that combines new data-aware techniques with deep neural network's error tolerance, making it well-suited for deep learning-based image recognition applications.

The group is led by Ken Takeuchi, professor at the Faculty of Science and Engineering, Chuo University presented the "Value-Aware SSD" at CICC 2017, a conference devoted to IC development tha was held April 30 - May 3, 2017, in Austin, Texas.

The new SSD features three memory control technologies and succeeded in realizing a high reliability, high speed and high image recognition accuracy that enable to withstand deep learning applications.

In image recognition systems, the characteristic vectors of an input image are compared with the characteristic vectors of a huge number of human images registered in the SSD.

One of the memory control technologies that the research group developed is "Value-Aware Data Mapping (VADM)." For example, in the case of 32-bit characteristic vectors, high-order bits have higher values than low-order bits.

Existing TLC (triple-level cell) flash memory is controlled so that the reliability of 3-bit data stored in each memory cell becomes the same. In case of the Value-Aware SSD, the value of reliability differs among "high-reliability bits," "intermediate-reliability bits" and "low-reliability bits." In addition, high-value data are stored in high-reliability memory cells, and low-value data are stored in low-reliability memory cells. As a result, even when there are 25x more memory errors than in the case of conventional SSDs, it becomes possible to realize a high recognition accuracy.

The researchers also developed the "Critical Page Error Reduction (CPER)" technology. To further improve the reliability of memory cells in which high-value data are stored, the group developed a method to modulate input data so that the state of the threshold voltage for recording high-value data is controlled and data are recorded while avoiding a low-reliability state. As a result, even when there are 19x more memory errors than in the case of the VADM, it is possible to achieve a high recognition accuracy.

Last but not least, what the researchers call "Accelerated LDPC (A-LDPC)" limits the number of the repeated decoding of the error correction circuit (ECC), which corrects the errors of memory cells at the time of reading out data, to five. As a result, the read speed was improved by 26%. At this point, some errors remain uncorrected, but the researchers say such errors do not affect the accuracy of image recognition.

Using the aforementioned technologies, the Value-Aware SSD with Vertical 3D-TLC (Triple-Level Cell) NAND flash increases the acceptable bit-error rate (BER) by 12-times compared to existing SSDs, improves the data-retention time by 300-times, and decreases the read time by 26%.