Intel and RISC-V backers announced rival alliances to support competing ecosystems around tomorrow’s processors.
Intel initiated Compute Express Link (CXL), an open chip-to-chip interconnect that it expects to use on its processors starting in 2021 to link to accelerators and memories. Other members include Alibaba, Cisco, Dell EMC, Facebook, Google, HPE, Huawei, and Microsoft.
Some RISC-V seperately proponents launched the CHIPS Alliance, a project of the Linux Foundation to develop a broad set of open-source IP blocks and tools for the instruction set architecture. Initial members include Esperanto, Google, SiFive, and Western Digital. CHIPS stands for Common Hardware for Interfaces, Processors, and Systems.
Compute Express Link
Intel together with Alibaba, Cisco, Dell EMC, Facebook, Google* Hewlett Packard Enterprise, Huawei and Microsoft today announced the founding of a consortium to develop Compute Express Link (CXL), an open interconnect technology that improves performance and removes the bottlenecks in computation-intensive workloads for CPUs and purpose-built accelerators.
Intel developed the technology behind CXL and donated it to the consortium to become the initial release of the new specification.
The explosion of data and rapid innovation in specialized workloads – like compression, encryption and artificial intelligence (AI) – have given rise to heterogeneous computing, where purpose-built accelerators work side-by-side with general-purpose CPUs. These accelerators need a high-performance connection to the processor, and, ideally, they share a common memory space to reduce overhead and latency. CXL is a technology that enables memory coherence between the accelerator and CPU, with very high bandwidth, and does so using well-understood infrastructure based on PCI Express Gen 5.
CXL creates a high-speed, low latency interconnect between the CPU and workload accelerators, such as GPUs, FPGAs and networking. CXL maintains memory coherency between the devices, allowing resource sharing for higher performance, reduced software stack complexity and lower overall system cost.
While there exist other interconnect protocols, Intel says that CXL is unique in delivering CPU/device memory coherence, reduced complexity on the device, and an standard physical and electrical interface together in a single technology.
The first-generation specification will be available to consortium members in the first half of this year. Expect to see products that incorporate CXL technology starting in Intel’s 2021 data center platforms, including Intel Xeon processors, FPGAs, GPUs and SmartNICs.
The Intel-led CXL competes head-on with a similar group called CCIX, launched in 2016 by Arm, AMD, IBM, and Xilinx. Both groups will use PCI Express as the basis for interconnects to which they add cache coherency.
CXL will start off using the 32-GT/s PCIe Gen 5, enabling PCIe I/O, cache-coherent processor links, and load/store memory semantics. Xilinx has already released one of the first chips using CCIX, initially based on today’s PCIe Gen 4.
The CHIPS Alliance is an ambitious effort and is just one of several open-hardware initiatives in the works at the Linux Foundation. CHIPS aims to create open-source blocks for a variety of embedded cores as well as multi-core SoCs capable of running Linux — and, ultimately, an open-source design flow to build and test them.
Fast interconnects are becoming increasingly important. Processors look to external accelerators and new memories to achieve performance gains as CMOS scaling slows.
Nvidia’s latest deep-learning systems use its proprietary NVLink to IBM Power 9 host processors. AMD designed its Infinity fabric to link its processors and GPUs, and IBM has its own OpenCAPI.
WD announced OmniXtend late last year, an open-source coherent interconnect based on an Ethernet PHY. The interconnect, along with the Swerv embedded core, will be WD’s initial contributions to the CHIPS Alliance.
The CHIPS Alliance aims to go beyond the work on the RISC-V ISA at the RISC-V Foundation to create a full library of open-source cores, blocks, and tools.
CHIPS also plans a project that will create and verify all the blocks needed for a multi-core RISC-V SoC that can run Linux. The work will be funded from membership fees that range from $25,000 to $2,500 a year. The blocks and tools will be available royalty-free under Apache and other licenses used by the Linux Foundation.
As their initial contributions, Google will submit a universal verification methodology for testing RISC-V chips, and SiFive will provide an unspecified design tool. Over the next decade, the group aims to assemble an entire open-source design flow for RISC-V.
The group’s initial focus will include leveraging existing open-source projects such as the Verilator simulator as well as some verification and synthesis tools. Some are being developed by universities as part of a DARPA project.