Recently established company SiPearl will be responsible for the development and marketing of the European Processor Initiative (EPI) project -- custom-made exascale-capable processors and technology that will be used to target the broader markets of AI, data analytics, edge computing, and autonomous vehicles.

Supported by the European Union, SiPearl will run the EPI project that has received funding from the European Union's Horizon 2020 research and innovation program.

High performance computing is crucial for meeting a growing range of increasingly complex strategic challenges. Historically used for research, weather forecasting, oil and gas prospecting, defense, chemicals and finance, etc., it has become essential for supporting the deployment of artificial intelligence, connected mobility, smart cities, bioengineering, cybersecurity, personalized medicine.

Europe faces two major issues: it is dependent on non-European technologies. While it uses more than one third of the world’s high performance computing resources, Europe produces less than 5% of them, and none of the microprocessors that equip its supercomputers are European. In addition, Europe's facilities have significantly lower capabilities than those in the United States and China. Number 6 in the global rankings, Europe’s most powerful supercomputer is seven times slower and its energy efficiency is two times lower than the world number 1-the Oak Ridge supercomputer in Tennessee.

The EPI consortium was selected to draw up, maintain and lead the roadmap for developing a range of high-performance, low-power microprocessors in Europe to equip supercomputers in particular.

The EPI project set out its initial roadmap, with a plan to ultimately produce a processor package that incorporates Arm general-purpose cores with a RISC-V-based accelerator, along with a number of more specialized coprocessors.

The first processor prototype will be manufactured on Taiwan Semiconductor Manufacturing Corp’s 6 nanometer extreme ultraviolet (EUV N6) process and is expected to tape-out by the end of 2020 or the beginning of 2021. Testing will probably commence in Q2 2021 and continue through Q4.

The EPI prototype will incorporate the Arm general-purpose processor, the RISC-V accelerator, Kalray’s MPPA and Menta’s eFPGA, as well as a cryptographic engine to support EU-specific sovereignty requirements.

This initial die will be part of a larger 2.5D interposer-based package that includes HBM memory, PCI-Express 5.0 links, plus interfaces to DDR memory. In subsequent implementations, the RISC-V and other accelerators could be split off into discrete dies and integrated into the package in the form of chiplets. But for now, everything will be etched on a single chip.

It’s still to be determined which accelerators and components make sense for the EU’s upcoming exascale supercomputers and how they will be apportioned across these machines.

Programming would be made possible with the use of OpenMP 5.0 which would offer an abstraction layer between the accelerator hardware and the application.

The RISC-V-based EPI accelerator (EPAC), code-named Titan, is itself of heterogeneous design, incorporating Vector Processing Units (VPUs) and Stencil/Tensor accelerators (STX). EPAC will support every standard numeric format from INT8 through FP64, as well as bfloat16. EPI is also looking into something called variable precision, where the number of bits devoted to processing is adapted at runtime depending on the desired precision.

The EPI project also plans to open up its hardware to other chipmakers by publishing the interface that glues the various components to one another.

The project’s goal is to ensure the first-generation of the HPC product is available to its system partners, Atos and E4 Computer Engineering, for testing and qualification. That should happen in the second half of 2021. The production hardware will then follow in the second half of 2022.

Recently established company SiPearl will be responsible for the development and marketing of the European Processor Initiative (EPI) project -- custom-made exascale-capable processors and technology that will be used to target the broader markets of AI, data analytics, edge computing, and autonomous vehicles.

Supported by the European Union, SiPearl will run the EPI project that has received funding from the European Union's Horizon 2020 research and innovation program.

High performance computing is crucial for meeting a growing range of increasingly complex strategic challenges. Historically used for research, weather forecasting, oil nd gas prospecting, defence, chemicals and finance, etc., it has become essential for supporting the deployment of artificial intelligence, connected mobility, smart cities, bioengineering, cybersecurity, personalised medicine.

Europe faces two major issues: it is dependent on non-European technologies. While it uses more than one third of the world’s high performance computing resources, Europe produces less than 5% of them, and none of the microprocessors that equip its supercomputers are European. In addition, Europe's facilities have significantly lower capabilities than those in the United States and China. Number 6 in the global rankings, Europe’s most powerful supercomputer is seven times slower and its energy efficiency is two times lower than the world number 1-the Oak Ridge supercomputer in Tennessee.

The EPI consortium was selected to draw up, maintain and lead the roadmap for developing a range of high-performance, low-power microprocessors in Europe to equip supercomputers in particular.

The EPI project set out its initial roadmap, with a plan to ultimately produce a processor package that incorporates Arm general-purpose cores with a RISC-V-based accelerator, along with a number of more specialized coprocessors.

The first processor prototype will be manufactured on Taiwan Semiconductor Manufacturing Corp’s 6 nanometer extreme ultraviolet (EUV N6) process and is expected to tape-out by the end of 2020 or the beginning of 2021. Testing will probably commence in Q2 2021 and continue through Q4.

The EPI prototype will incorporate the Arm general-purpose processor, the RISC-V accelerator, Kalray’s MPPA and Menta’s eFPGA, as well as a cryptographic engine to support EU-specific sovereignty requirements.

This initial die will be part of a larger 2.5D interposer-based package that includes HBM memory, PCI-Express 5.0 links, plus interfaces to DDR memory. In subsequent implementations, the RISC-V and other accelerators could be split off into discrete dies and integrated into the package in the form of chiplets. But for now, everything will be etched on a single chip.

It’s still to be determined which accelerators and components make sense for the EU’s upcoming exascale supercomputers and how they will be apportioned across these machines.

Programming would be made possible with the use of OpenMP 5.0 which would offer an abstraction layer between the accelerator hardware and the application.

The RISC-V-based EPI accelerator (EPAC), code-named Titan, is itself of heterogeneous design, incorporating Vector Processing Units (VPUs) and Stencil/Tensor accelerators (STX). EPAC will support every standard numeric format from INT8 through FP64, as well as bfloat16. EPI is also looking into something called variable precision, where the number of bits devoted to processing is adapted at runtime depending on the desired precision.

The EPI project also plans to open up its hardware to other chipmakers by publishing the interface that glues the various components to one another.

The project’s goal is to ensure the first-generation of the HPC product is available to its system partners, Atos and E4 Computer Engineering, for testing and qualification. That should happen in the second half of 2021. The production hardware will then follow in the second half of 2022.