Tilera Releases 64-Core Embedded Processor
Tilera Corporation today launched the TILE64 processor, the first in a family of Tile Processor chips based on a revolutionary architecture that can scale to hundreds and even thousands of cores.
The TILE64 processor contains 64 full-featured, programmable cores - each capable of running Linux - and delivers 10X the performance and 30X the performance-per-watt of the Intel dual-core Xeon, and 40X the performance of the Texas Instruments DSP, according to the company's announcement. Initial target markets for the TILE64 processor include the embedded networking and digital multimedia markets.
Tilera was founded in 2004 to bring to market the MIT research of Dr. Anant Agarwal who first created the mesh-based multicore architecture in 1996. The "Raw" project received multi-million dollar DARPA and National Science Foundation grants and spawned the development of the first tiled multicore processor prototype and associated multicore software in 2002.
"This is the first significant new chip architectural development in a decade," said Tilera President and C.E.O., Devesh Garg. "We developed this new architecture because existing multicore technologies simply cannot scale beyond a handful of cores. Moreover, customers have repeatedly indicated that the current multicore software tools are very primitive because they are based on single-processor-core models. We're introducing a revolutionary hardware and software platform that has solved the fundamental challenges associated with multicore scalability."
Tilera's iMesh Interconnect
Tilera's new architecture promises to offer superior performance because it eliminates the on-chip bus interconnect, a kind of centralized intersection that information must flow through between cores within the chip, or before it leaves the chip. As engineers have added more cores to chips, the bus has created an information traffic jam because packets from these cores all must travel to one central point, like a spoke-and-wheel traffic intersection in an old city.
Tilera's technology eliminates the bus by placing a communications switch on each processor core and arranging them in a grid fashion on the chip. This creates an efficient 2-dimensional traffic system for packets, much like the layout of a modern city's streets. Tilera's implementation of this grid architecture is called iMesh (intelligent Mesh), and it incorporates a number of patented innovations that enhance the performance and flexibility of the mesh. Because the aggregate bandwidth is orders of magnitude greater than a bus and the distance between cores is shorter, the iMesh technology can be leveraged to create grids as large or small as an application requires, creating a "computing-by-the-yard" scalability, with breakthrough performance and ultra-low power consumption.
The TILE64 Processor Specifications
Each of the 64 cores on the TILE64 processor is capable of running its own operating system, such as Linux. Each core is a full-featured, general-purpose processor that includes L1 and L2 caches, as well as a distributed L3 cache. The cores are overlaid with the iMesh network, which provides extremely low-latency, high bandwidth communications between the cores, memory and the I/O.
In order to minimize total system power, cost and real estate, the TILE64 processor integrates four DDR2 memory controllers and a complete array of high speed I/O interfaces, including two 10 Gbps XAUI, two 10 Gbps PCIe, two 1 Gbps Ethernet RGMII, and a programmable flexible I/O interface to support interfaces such as compact flash and disk drives.
"The TILE64 processor is suited for high performance embedded system markets. In the networking and telecommunications areas, the TILE64 processor is designed into switches and security appliances to provide unmatched performance of up to 20 Gbps of L4-L7 services. In the digital video and multimedia market, the TILE64 delivers an unprecedented two streams of broadcast-quality, high-definition H.264-encode capability in a single chip, and more than ten streams of encode for high-definition video conferencing applications," Tillera's announcement reads.
The TILE64 processor is available now in three different device variants based on frequency and I/O capabilities. Production pricing for the TILE64 family starts at $435 in 10K unit quantities. Tilera's roadmap also includes plans for a 36-core and a 120-core device.
Tilera was founded in 2004 to bring to market the MIT research of Dr. Anant Agarwal who first created the mesh-based multicore architecture in 1996. The "Raw" project received multi-million dollar DARPA and National Science Foundation grants and spawned the development of the first tiled multicore processor prototype and associated multicore software in 2002.
"This is the first significant new chip architectural development in a decade," said Tilera President and C.E.O., Devesh Garg. "We developed this new architecture because existing multicore technologies simply cannot scale beyond a handful of cores. Moreover, customers have repeatedly indicated that the current multicore software tools are very primitive because they are based on single-processor-core models. We're introducing a revolutionary hardware and software platform that has solved the fundamental challenges associated with multicore scalability."
Tilera's iMesh Interconnect
Tilera's new architecture promises to offer superior performance because it eliminates the on-chip bus interconnect, a kind of centralized intersection that information must flow through between cores within the chip, or before it leaves the chip. As engineers have added more cores to chips, the bus has created an information traffic jam because packets from these cores all must travel to one central point, like a spoke-and-wheel traffic intersection in an old city.
Tilera's technology eliminates the bus by placing a communications switch on each processor core and arranging them in a grid fashion on the chip. This creates an efficient 2-dimensional traffic system for packets, much like the layout of a modern city's streets. Tilera's implementation of this grid architecture is called iMesh (intelligent Mesh), and it incorporates a number of patented innovations that enhance the performance and flexibility of the mesh. Because the aggregate bandwidth is orders of magnitude greater than a bus and the distance between cores is shorter, the iMesh technology can be leveraged to create grids as large or small as an application requires, creating a "computing-by-the-yard" scalability, with breakthrough performance and ultra-low power consumption.
The TILE64 Processor Specifications
Each of the 64 cores on the TILE64 processor is capable of running its own operating system, such as Linux. Each core is a full-featured, general-purpose processor that includes L1 and L2 caches, as well as a distributed L3 cache. The cores are overlaid with the iMesh network, which provides extremely low-latency, high bandwidth communications between the cores, memory and the I/O.
In order to minimize total system power, cost and real estate, the TILE64 processor integrates four DDR2 memory controllers and a complete array of high speed I/O interfaces, including two 10 Gbps XAUI, two 10 Gbps PCIe, two 1 Gbps Ethernet RGMII, and a programmable flexible I/O interface to support interfaces such as compact flash and disk drives.
"The TILE64 processor is suited for high performance embedded system markets. In the networking and telecommunications areas, the TILE64 processor is designed into switches and security appliances to provide unmatched performance of up to 20 Gbps of L4-L7 services. In the digital video and multimedia market, the TILE64 delivers an unprecedented two streams of broadcast-quality, high-definition H.264-encode capability in a single chip, and more than ten streams of encode for high-definition video conferencing applications," Tillera's announcement reads.
The TILE64 processor is available now in three different device variants based on frequency and I/O capabilities. Production pricing for the TILE64 family starts at $435 in 10K unit quantities. Tilera's roadmap also includes plans for a 36-core and a 120-core device.
