Toshiba Memory Corp. has developed a small bridge chip that offers high-speed and increases the capacity of SSDs.
Using bridge chips with a small occupied area and low-power consumption, the company has managed to connect more flash memory chips with fewer high-speed signal lines than with conventional methods.
The approach was announced in San Francisco on February 20, at the International Solid-State Circuits Conference 2019 (ISSCC 2019).
In SSDs, multiple flash memory chips are connected to a controller that manages their operation. As more flash memory chips are connected to a controller interface, operating speed degrades, so there are limits to the number of chips that can be connected. In order to increase capacity, it is necessary to increase the number of interfaces, but that results in an enormous number of high-speed signal lines connected to the controller, making it more difficult to implement the wiring on the SSD board.
Toshiba has overcome this problem with the development of a bridge chip that connects the controller and flash memory chips, using three techniques: a daisy chains connection including the controller and bridge chips in a ring shape; a serial communication using 4-level Pulse Amplitude Modulation (PAM 4); and a jitter improvement technique for eliminating a PLL circuit Phase Locked Loop - a circuit that generates an accurate reference signal) in the bridge chips. By using these techniques the overhead of the bridge chips is reduced, and it is possible to operate a large number of flash memory chips at high speed with only a few high-speed signal lines.
The ring-shape configuration of the bridge chips and the controller reduces the number of transceivers required in the bridge chip from two pairs to one pair, it achieves chip area reduction of the bridge chip. In addition, adopting PAM 4 serial communication between the controller and the daisy-chained bridge chips lowers the operating speed in the bridge chips’ circuits and relaxes their required performance. A new Clock Data Recovery (CDR - a circuit that recovers the data and clock from the received signal) that utilizes the characteristics of PAM 4 to improve jitter characteristics eliminates the need for a PLL circuit in the bridge chip, which also contributes to a smaller chip area and lower power consumption.
The prototype bridge chips were fabricated with 28nm CMOS process, and the results were evaluated by connecting four bridge chips and a controller in ring-shape daisy chain. This confirmed satisfactory performance of PAM 4 communication by all of the bridge chips and the controller at 25.6 Gbps, and also that it is possible to obtain a Bit Error Rate (BER - the lower value is the better performance) of less than 10-12.
Moving forward, the company will continue development work toward achieving high-speed, large-capacity storage by further enhancing bridge-chip performance while reducing the chip’s area and power consumption.