SK Hynix detailed its first synchronous DRAM chip based on the DDR5 specification at the International Solid State Circuits Conference in San Fransisco.

The Jedec standards organization has not yet finaluized the specifications of the DDR5 — or Double Data Rate 5 - and the DDR5 products are expected to appear beginning late this year.

The memory offers double the bandwidth and double the density of DDR4 along with delivering improved channel efficiency.

Speaking on behalf of Hynix, Dongkyun Kim presented the ISSCC paper Wednesday on the Hynix DDR5 chip, a 16Gb 6.4Gb/s/pin SDRAM that runs at 1.1V and measures 76.22mm2. The device is fabricated in a 1ynm, 4-metal DRAM process.

Kim described the implementation of a modified delay-locked loop (DLL) using a phase rotator and an injection locked oscillator to reduce clock jitter and clock duty cycle distortion associated with operating at higher clock speeds. He also described other techniques used by the Hynix design team, including a write-level training method to offset clock-domain issues associated with higher speeds and a modified forward feedback equalization (FFE) circuit.

Rival South Korean Samsung Electronics also countered in the same session by describing the implementation of an SDRAM process based on the low-power flavor of the spec, LPDDR5. The company talked about a a 10nm-class LPDDR5 SDRAM capable of up to 7.5Gb/s at 1.05V.

Designed for smartphones, tablets and ultra-thin notebooks, LPDDR5 has been recently standardized by Jedec. LPDDR5 will will eventually operate at an I/O rate of 6400 MT/s, 50% higher than that of the first version of LPDDR4.