Collaborative efforts are focused on TSMC's 16FF+ process technology which will deliver an additional 11% gain in performance for the Cortex-A57 at the same power as the 16FF process, along with a further 35% power reduction for the Cortex-A53 when running low-intensity applications. This further increases the dynamic performance range and power savings for big.LITTLE platforms. 16FF+ is scheduled to be delivered by Q4 2014. Early big.LITTLE implementations of Cortex-A57 and Cortex-A53 processors on 16FF+ are supported by ARM POP IP technology.
ARM and TSMC will be presenting detailed results of this collaboration at TSMC's OIP Ecosystem Forum at the San Jose Convention Center on Sept. 30, 2014; and ARM TechCon at the Santa Clara Convention Center on Oct. 2, 2014.