The 40nm process is one of the semiconductor industry?s most advanced available for production manufacturing process and is expected to play a key role in the development of next generation products in global consumer electronics, mobile, and computer end markets.
"We view 40nm as an important process node for the cost-effective development of graphics chips and other devices, especially in 2009," said Rick Bergman, Senior Vice-President & General Manager, Graphics Products Group.
"Today designers are faced with the challenge of increasing the functionality of their product while not increasing power consumption. By rolling out the industry?s most advanced programmable logic devices at 40-nm, we are enabling designers to quickly achieve new levels of integration and innovation, while staying within their power budgets," said Bill Hata, Altera senior vice president of Worldwide Operations and Engineering.
TSMC?s 40nm G and the 40nm low power (LP) manufacturing processes timetables were formally announced in March this year. The 40G process targets performance-driven applications including computer processor chips, GPU (graphic processing units), game consoles, networking applications, field programmable gate arrays (FPGA), hard disc drive, and other devices. The 40LP process targets low-power applications including cellular baseband, application processors, portable consumer and wireless connectivity devices.
TSMC?s 40nmG and 40nm LP processes both passed process qualification, reaching "first wafers out" status as planned and completed product qualification in October when first customer wafers entered production. As with every TSMC process node, the 40G and 40LP processes offer a full range of mixed-signal and RF options, along with embedded memory to support a broad range of analogy/RF-intensive and memory-rich applications.
Multiple customers at 40nm have adopted Reference Flow 9.0, a production-proven design infrastructure that allows designers to take full advantage of 40G and 40LP processes. TSMC?s Reference Flow includes a number of power reduction techniques and tools that allow designers considering 45nm design rules to transparently target their designs to 40nm processes without explicitly dealing with a multitude of scaling factors. Reference Flow also facilitates enhanced timing, statistical design and design for manufacturing (DFM).
TSMC claism that the 40G and 40LP processes offer designers up to a 2.35 times raw gate density improvement over the 65nm node. The 40G process is up to 30% faster than TSMC?s 65nm GP process at the same leakage, or up to 70% lower leakage at the same speed. In addition, it provides up to 45% lower active power than the 65GP process. The 40LP process provides up to 46% lower leakage and up to 50% lower active power than TSMC?s 65LP at the same speed. It also features the smallest SRAM cell size, 0.242um2, and macro size in production today.
Besides 40-nm, TSMC is leading in other processes. In September, the company rolled out its 32- and 28-nm processes. The 32-nm process is a cost-down version of its 40-nm technology, while 28-nm is considered by TSMC as a "full-node" offering.
At 28-nm, TSMC plans to offer two separate options for the gate stack: conventional silicon oxynitride (SiON) and a high-k/metal-gate technology. But at 32-nm, the company will only offer a SiON for the gate stack.