Western Digital announced at the RISC-V Summit three new open-source innovations designed to support Western Digital's internal RISC-V development efforts and those of the RISC-V ecosystem.
WD currently uses one billion cores every year in its products, and the company is committed to transition its processor cores to RISC-V - an open, scalable instruction set architecture (ISA). While working to incorporate RISC-V cores into its own products, WD is also working to develop the supporting ecosystem.
In his keynote address, Western Digital's Chief Technology Officer Martin Fink unveiled plans to release a new open source RISC-V core, an open standard initiative for cache coherent memory over a network and an open source RISC-V instruction set simulator. WD hopes that these innovations will accelerate development of new open, purpose-built compute architectures for Big Data and Fast Data environments.
"As Big Data and Fast Data continues to proliferate, purpose-built technologies are essential for unlocking the true value of data across today's wide-ranging data-centric applications," said Fink. "Our SweRV Core and the new cache coherency fabric initiative demonstrate the significant possibilities that can be realized by bringing data closer to processing power. These planned contributions to the open-source community and continued commitment of the RISC-V initiative offer exciting potential to accelerate collaborative innovation and data-driven discoveries."
Western Digital is planning to open source its new RISC-V SweRV Core, which has a 2-way superscalar design. Western Digital's RISC-V SweRV Core is a 32-bit, 2-way superscalar, 9 stage pipeline core that allows several instructions to be loaded at once and execute simultaneously, shortening the time taken to run programs. With an expected simulation performance of up to 4.9 CoreMarks/Mhz and small footprint, it offers capabilities for embedded devices supporting data-intensive edge applications, such as storage controllers, industrial IoT, real-time analytics in surveillance systems, and other smart systems.
The 4.9 CoreMarks/Mhz score beats many in-order and some out-of-order cores from Arm, MIPS, and others.
Its design offers clock speeds of up to 1.8Ghz on a 28mm CMOS process technology. The company plans to use the SweRV Core in various internal embedded designs, including flash controllers and SSDs. Open sourcing the core is expected to drive development of new data-centric applications such as Internet of Things (IoT), secure processing, industrial controls and more.
Western Digital's OmniXtend is a new open approach to providing cache coherent memory over an Ethernet fabric. This memory-centric system architecture provides open standard interfaces for access and data sharing across processors, machine learning accelerators, GPUs, FPGAs and other components. It is an open solution for attaching persistent memory to processors and offers potential support of future advanced fabrics that connect compute, storage, memory and I/O components.
The company aims to support whatever interfaces its customers want. However, it does want to enable an open alternative to Intel’s Omnipath and DDR-T, interfaces that are proprietary to its x86 processors.
The first implementation of OmniXtend is expected by June, using a prototype board from WD, a RISC-V core from SiFive and an Ethernet switch from Barefoot Networks running code written in the P4 language. The company did not release the target bandwidth or data rate of the design.
Western Digital also introduced today its open-sourced SweRV Instruction Set Simulator (ISS), which offers full test bench support for use with RISC-V cores. An ISS is a computer program that simulates the execution of instructions of a processor. It allows external events to be modeled, such as interrupts and bus errors, and assures the RISC-V core is functioning properly. The company utilized the SweRV ISS to simulate and validate the SweRV Core, with more than 10 billion instructions executed. Western Digital expects both the SweRV Core and SweRV ISS will help to accelerate the industry's move to an open source instruction set architecture.
Western Digital's SweRV core will be available in CY Q1 2019.
More from the RISC-V annual summit
Besides WD, the Microsemi division of Microchip described at the RISC-V annual summit a five-core complex that it will embed in its PolarFire FPGAs by early 2020. The chip marks its first step in a plan to standardize on use of RISC-V.
Microsemi will embed a five-core RISC complex in its mid-range product, creating the PolarFire FPGA SoC line, taping out mid-2019. Four of the cores sport memory-management and floating-point units for Linux; the fifth lacks those blocks and is aimed at running an RTOS.
Microsemi worked with SiFive to tailor the cores and their 2-MByte L2 caches that can also be configured as scratchpads or direct-access memories. The cores had enhancements to support more deterministic performance than typical application processors.
For security, the memories support single-error correction and double-error detection and physical memory protection. The block includes a differential power analysis safe crypto core, a defense-grade secure boot, and 128 Kbits of flash boot read-only memory.
Like most FPGAs, Microsemi expects that the products will find use in a wide swath of markets from aerospace and defense missiles and radios to portable medical and test gear, industrial cameras, and wireless remote radio heads.
The PolarFire products generally support up to 500,000 logic elements and up to 12.7G SerDes. They aim to deliver lower power consumption and cost than similarly configured Xilinx Kintex and Artix parts.
A developer’s kit is available for engineers who want to start designs before chips are generally available in early 2020. Microsemi ported a range of operating systems to the cores, including FreeRTOS, Huawei, Micrium, and Zephyr RTOSes.
In the field of machine learning, startup SiFive described two RISC-V chips — an embedded inference device based on Nvidia’s Deep Learning Accelerator and a training chip using newly mined RISC-V vector extensions along with HBM2 memory and 56-Gbit/s SerDes.
Google, an early member of the RISC-V Foundation, showed its TensorFlow Lite software geared for embedded systems running on the Zephyr operating system on a RISC-V chip. Bitmain, a leader in bitcoin-mining silicon, revealed that its Sophon Edge AI chip announced last year uses a RISC-V core as its sensor hub.
Korean startup Fadu described an SSD controller made in a 7-nm process and based on a 64-bit RISC-V core. Startup Esperanto, which debuted at a RISC-V workshop last year, described its ET-Maxion, a high-frequency, out-of-order RISC-V core being designed for TSMC’s 7-nm process.
Beyond the summit in Silicon Valley, two RISC-V alliances have already formed in China. One includes large corporations such as Alibaba, Great Dragon Telecom, Huawei, and ZTE and is expected to create cores. Another is expected to focus on tools and practices for integrating cores into SoCs.
Over the last several years, China has acquired access to most major processor architectures through joint ventures with companies including AMD for the x86, Qualcomm for Arm, and IBM for Power. To date, some China server makers say that they continue to prefer more mature U.S. sources, but that could change.
RISC-V has a very small slice of the processor IP market that Arm dominates today, with 21.3 billion units shipped in 2017. However, it is gaining steam to embedded, automotive, and IoT apps that are tolerant of its lack of broad support from third-party software.