NEC Develop 32Mb MRAM for Embedding in SoCs
NEC has announced the successful operational demonstration of a 32Mb MRAM (Magnetic Random Access Memory) that can be embedded in SoCs.
NEC and NEC Electronics have reduced the area of control circuits in the 32Mb MRAM design in order to achieve superior cell efficiency that enables 73% of a memory macro's area to be allocated to memory cells.
This innovative demonstration supports the possibility of applying high speed MRAM technologies to system LSIs, which is required in order to embed larger capacity MRAM macros with larger sized cells.
Power consumption of system LSIs tends to increase in relation to greater functionality and the number of transistors. However, the need for lowering power consumption of electronic appliances that use system LSIs is becoming increasingly strong. In order to reduce the power consumption of system LSIs, it is most effective for LSIs to enter into a standby state where their power is cut off. Therefore, usable non-volatile memory macros embedded in system LSIs are also in demand.
In November 2007 NEC developed a high speed 250MHz, 1Mb MRAM macro suitable for embedding in system LSIs. However, since the memory cell of the high speed 1Mb MRAM macro consists of two transistors and one MTJ, enlarging its memory capacity is more challenging than increasing the memory of MRAM macro equipped with just one transistor and one MTJ cell.
The latest demonstrations adapted MRAM macro cell arrays with NEC's newly developed write circuits to achieve macro cell efficiency of 73%. This both reduced MRAM macro size and enlarged memory capacity.
The macro's word line decoder circuit was equipped with a word boost circuit in order to shrink memory cell area. However, word boost circuits are prone to delay and tend to extend the cycle time of macros. To solve this problem, a word boost circuit featuring optimized conversion levels was developed. Accordingly, the high speed operation cycle time of 9ns was achieved despite being a large capacity 32Mb macro.
To demonstrate its operation in a system board, the 32Mb MRAM chip has a protocol transform circuit between the MRAM macro and I/O buffer circuits. The MRAM is compatible with an asynchronous SRAM. By changing the protocol transform circuit, MRAM becomes compatible with any kind of memory.
The successful operating demonstration of the 32Mb MRAM indicates that MRAM macros using high speed MRAM cells are, in fact, able to enlarge their capacity. It also widens the field of application for system LSIs where memory macros are substituted for MRAMs. Looking forward, NEC is aiming to demonstrate an SoC integrated with large capacity, high speed MRAM macros.
NEC and NEC Electronics' research is partially supported by the New Energy and Industrial Technology Development Organization's (NEDO) MRAM technology development project for the realization of high-speed/non-volatile memory embedded in system LSIs.
NEC and NEC Electronics presented the results of this research on February 11th at the IEEE International Solid State Circuits Conference (ISSCC 2009), held in San Francisco, California, U.S.A.
Power consumption of system LSIs tends to increase in relation to greater functionality and the number of transistors. However, the need for lowering power consumption of electronic appliances that use system LSIs is becoming increasingly strong. In order to reduce the power consumption of system LSIs, it is most effective for LSIs to enter into a standby state where their power is cut off. Therefore, usable non-volatile memory macros embedded in system LSIs are also in demand.
In November 2007 NEC developed a high speed 250MHz, 1Mb MRAM macro suitable for embedding in system LSIs. However, since the memory cell of the high speed 1Mb MRAM macro consists of two transistors and one MTJ, enlarging its memory capacity is more challenging than increasing the memory of MRAM macro equipped with just one transistor and one MTJ cell.
The latest demonstrations adapted MRAM macro cell arrays with NEC's newly developed write circuits to achieve macro cell efficiency of 73%. This both reduced MRAM macro size and enlarged memory capacity.
The macro's word line decoder circuit was equipped with a word boost circuit in order to shrink memory cell area. However, word boost circuits are prone to delay and tend to extend the cycle time of macros. To solve this problem, a word boost circuit featuring optimized conversion levels was developed. Accordingly, the high speed operation cycle time of 9ns was achieved despite being a large capacity 32Mb macro.
To demonstrate its operation in a system board, the 32Mb MRAM chip has a protocol transform circuit between the MRAM macro and I/O buffer circuits. The MRAM is compatible with an asynchronous SRAM. By changing the protocol transform circuit, MRAM becomes compatible with any kind of memory.
The successful operating demonstration of the 32Mb MRAM indicates that MRAM macros using high speed MRAM cells are, in fact, able to enlarge their capacity. It also widens the field of application for system LSIs where memory macros are substituted for MRAMs. Looking forward, NEC is aiming to demonstrate an SoC integrated with large capacity, high speed MRAM macros.
NEC and NEC Electronics' research is partially supported by the New Energy and Industrial Technology Development Organization's (NEDO) MRAM technology development project for the realization of high-speed/non-volatile memory embedded in system LSIs.
NEC and NEC Electronics presented the results of this research on February 11th at the IEEE International Solid State Circuits Conference (ISSCC 2009), held in San Francisco, California, U.S.A.
