GLOBALFOUNDRIES today announced the availability of its 7nm Leading-Performance (7LP) FinFET semiconductor technology, delivering a 40 percent generational performance boost to meet the needs of applications such as mobile processors, cloud servers and networking infrastructure.

The company claims it exceeds targets although it is about six months behind its chief rival, TSMC. The company is offering design kits now, and expects the first products based on 7LP to launch in the first half of 2018, with volume production ramping in the second half of 2018.

"Our 7nm FinFET technology development is on track and we are seeing strong customer traction, with multiple product tapeouts planned in 2018," said Gregg Bartlett, senior vice president of the CMOS Business Unit at GF. "And, while driving to commercialize 7nm, we are actively developing next-generation technologies at 5nm and beyond to ensure our customers have access to a world-class roadmap at the leading edge."

GF’s 7LP process will initially use immersion steppers to pack more than 17 million gates/mm2. It reduces die cost by more than 30 percent based on more than a 50 percent shrink from its 14nm node based on fully laid-out chips.

GF also continues to invest in research and development for next-generation technology nodes. In collaboration with its partners IBM and Samsung, the company announced a 7nm test chip in 2015, followed by the recent announcement of the demonstration of a functioning 5nm chip using silicon nanosheet transistors.

To accelerate the 7LP production ramp, GF is investing in new process equipment capabilities, including the addition of the first two EUV lithography tools in the second half of this year. The initial production ramp of 7LP will be based on an optical lithography approach, with migration to EUV lithography when the technology is ready for volume manufacturing.

GLOBALFOUNDRIES hopes mask defect levels for EUV systems are low enough by 2020 to use the systems to make metal layers. A mask defect the size of a golf ball in California can kill a design, branding the problem as the only red light on the horizon for EUV today.

ASML has developed a polysilicon pellicle and the Imec research institute is working on a nanotube-based pellicle to protect masks from contamination during processing. The pellicles can absorb more than 30 percent of the EUV light, lowering throughput.

GLOBALFOUNDRIES has also made available FX-7, an application-specific integrated circuit (ASIC) offering built on the company's 7nm FinFET process technology. FX-7 is an integrated design platform that combines leading-edge manufacturing process technology with a differentiated suite of intellectual property and 2.5D/3D packaging to deliver a complete solution for data center, machine learning, automotive, wired communications, and 5G wireless applications.

The FX-7 provides a suite of tailored interface IPs including High Speed SerDes (60G, 112G), differentiated memory solutions including low-voltage SRAM, high-performance embedded TCAM, integrated DACs/ADCs, ARM processors, and advanced packaging options such as 2.5D/3D.

Design kits for the FX-7 ASIC offering are now available, with volume production expected in 2019.

Rival TSMC said in March it expected to complete in May the first of about a dozen 7nm tapeouts this year. It expects its process will deliver 3.3x greater routed gate density and either 35 percent more speed or 60 percent less power than the foundry's 16FF+ node.

At IEDM late last year, Samsung showed 7nm designs sporting FinFETs with 44-48nm contacted polysilicon pitch and 36nm metal pitch. In March, Intel said its 10nm process now in production supports 36nm minimum metal pitches, 34nm fin pitches and 54nm gate pitches and has a density of 100.8 million transistors/mm2.

GLOBALFOUNDRIES's executives do not advertising what their pitches are, and are just saying they have a "very competitive base 7nm offering."

Samsung said it will use EUV lithography at 7nm, a move that means its node may not be ready until 2019. However it also announced in May plans for an 8nm node and made its foundry a separate business unit, potentially preparing it for a spin out.

Looking ahead, GLOBALFOUNDRIES foresees the 7nm FinFET extended quite a ways, but whether it will be called a 6 or 5nm node remains to be seen. Future processes will employ a mix of transistor types, something an Imec executive predicted last month. Gate-all-around transistors will be needed for a "full 5nm" node.