Intel did not disclose terms of the deal for eASIC, which is based in Santa Clara, California.
"It's a small company today but we believe we can scale it and make it a real differentiator over Xilinx," Intel's larger rival in FPGAs, said Dan McNamara, general manager of Intel's Programmable Solutions Group, formerly Altera.
eASIC defined a proprietary approach for taking a wafer with pre-defined logic and memory and customizing it with interconnects in just one or two mask layers. The resulting structured ASIC has a fraction of the up-front cost of a full ASIC although it lacks its programmability. At one time, Intel and LSI Logic were among rivals offering roughly similar approaches.
eASIC could be offering Arm cores early next year. Longer term, its next-generation products could offer Intel's Embedded Multi-Die Interconnect Bridge (EMIB), a proprietary die-to-die package that is a low-cost rival to 2.5D chip stacks.
So far, Intel's only public products using EMIB have been its FPGAs that employed it as a bridge to serdes, HBM memory stacks and Xeon processors.